Semiconductor device and ic card

ABSTRACT

Wiring lines for the supply of a voltage to feed a drive voltage to an integrated circuit formed in a semiconductor chip are disposed so as to cover a main surface of the semiconductor chip, so that, if the wiring lines are removed for the purpose of analyzing information stored in the semiconductor chip, the integrated circuit does not operate and it is impossible to analyze the information. Further, there is provided a processing detector circuit for detecting that the wiring lines have been tampered with. When the processing detector circuit detects a change in the state of the wiring lines, the integrated circuit is reset. Thus, it is possible to improve the security of information stored on the card.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device and an IC(Integrated Circuit) card technique. Particularly, the present inventionis concerned with a technique which is applicable to the improvement ofsecurity for information stored in a semiconductor device.

BACKGROUND OF THE INVENTION

[0002] In an IC card which the present inventors have studied, thereading and writing of data from and to memory are managed by thefunction of a CPU (Central Processing Unit) incorporated in the IC card,and a high security function is ensured in which a cipher processing isexecuted by the card itself. Further, its memory capacity is 30 to 100times larger than that of a magnetic card. Thus, the IC card in questionis expected to see considerable use as an information storage medium invarious fields, including finance, distribution, medical care, traffic,transportation, and education. In a general IC card structure, a recessis formed in part of a plastic sheet, which is about the size of a nameor business card, and a packaged semiconductor chip is embedded therein.As a top layer of the semiconductor chip, there is a surface protectingfilm formed of an insulating material so as to cover the whole of themain surface of the semiconductor chip. Wiring lines, such as bus linesand control lines arranged on the main surface of the semiconductor chipare covered with an overlying multi-layer interconnection.

[0003] A technique for improving the information security of asemiconductor device is described, for example, in Japanese UnexaminedPatent Publication No. Hei 11 (1999)-145401, which technique involvesthe provision of a conductor layer serving as a shield layer thatoverlies and covers the semiconductor element so as to prevent access tothe wiring lines thereof. However, the present inventors have found thatthe following problems are inherent in the IC card security techniquedescribed in this publication.

[0004] One problem with the above-described security technique is that,if the semiconductor device is operated after removing the whole of theshield layer with a chemical and if, in this state, a needle foranalysis is brought into direct contact with a bus line or a signalline, it is possible to analyze information stored in the semiconductordevice. In addition, although bus lines and signal lines are coveredwith the multi-layer interconnection, an uncovered gap will typicallyoccur in an input port of a module or the like in relation to the layoutof the power supply wiring. There may occur a case where informationstored in the semiconductor device can be analyzed by the application ofan analyzing needle through such a gap.

[0005] It is an object of the present invention to provide a techniquefor improving the security of information stored in a semiconductordevice.

[0006] The above and other objects and novel features of the presentinvention will become apparent from the following description and theaccompanying drawings.

SUMMARY OF THE INVENTION

[0007] Typical features of the invention as disclosed herein will beoutlined below.

[0008] According to the present invention, if a predetermined wiringline which overlies a semiconductor chip is removed or cut, it becomesimpossible to analyze information stored in the semiconductor chip.

[0009] According to the present invention, a processing detector circuitis provided for detecting the processing of a predetermined wiring linewhich overlies a semiconductor chip.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 is a plan view of an IC card (a semiconductor device)according to a first embodiment of the present invention;

[0011]FIG. 2 is a sectional view taken on line X1-X1 in FIG. 1;

[0012]FIG. 3 is a sectional view taken on line X1-X1 in FIG. 1 in an ICcard according to a modification of the structure of FIG. 2;

[0013]FIG. 4 is a plan view of a semiconductor chip which constitutesthe IC card of FIG. 1;

[0014]FIG. 5 is a plan view of a principal portion of an element area ona main surface of the semiconductor chip;

[0015]FIG. 6 is a sectional view of a principal portion of thesemiconductor chip;

[0016]FIG. 7 is a plan view of a semiconductor chip which constitutes anIC card (a semiconductor device) according to a second embodiment of thepresent invention;

[0017]FIG. 8 is a plan view of a semiconductor chip which constitutes anIC card according to a third embodiment of the present invention;

[0018]FIG. 9 is a plan view of a semiconductor chip which constitutes anIC card according to a fourth embodiment of the present invention;

[0019]FIG. 10 is a sectional view taken on line X3-X3 in FIG. 9;

[0020]FIG. 11 is a plan view of a semiconductor chip which constitutesan IC card according to a fifth embodiment of the present invention;

[0021]FIG. 12 is a plan view of a semiconductor chip which constitutesan IC card according to a sixth embodiment of the present invention;

[0022]FIG. 13 is a schematic circuit diagram showing an example of aprocessing detector circuit illustrated in FIG. 12;

[0023]FIG. 14 is a diagram which illustrates the operation of theprocessing detector circuit illustrated in FIG. 13;

[0024]FIG. 15 is an enlarged plan view of a principal portion of thesemiconductor chip illustrated in FIG. 12;

[0025]FIG. 16 is a sectional view taken on line X4-X4 in FIG. 15;

[0026]FIG. 17 is a diagram showing an example of the connectionconfiguration of a processing detector circuit in an IC card accordingto a seventh embodiment of the present invention;

[0027]FIG. 18 is a plan view of the main surface of the semiconductorchip shown in FIG. 4;

[0028]FIG. 19 is a plan view of a semiconductor chip which constitutes asemiconductor device according to an eighth embodiment of the presentinvention;

[0029]FIG. 20 is a diagram of a shield disposed on the semiconductorchip shown in FIG. 19;

[0030]FIG. 21 is an enlarged plan view of a principal portion of FIG.20;

[0031]FIG. 22 is a developed perspective view of a layout layerstructure of a semiconductor device according to a ninth embodiment ofthe present invention;

[0032]FIG. 23 is a plan view of a principal portion of FIG. 22;

[0033]FIG. 24 is a plan view corresponding to FIG. 23, in which wiringlines having a shielding function are removed;

[0034]FIG. 25 is a diagram showing an example of subdivision of a shieldarea;

[0035]FIG. 26 is a plan view showing an example of wiring for an activeshield;

[0036]FIG. 27 is a plan view showing another example of wiring for anactive shield;

[0037]FIG. 28 is a plan view showing a further example of wiring for anactive shield;

[0038]FIG. 29 is a plan view showing a still further example of wiringfor an active shield;

[0039]FIG. 30 is a plan view showing an example of the wiring layout foran active shield in each of the subdivided areas of the shield area;

[0040]FIG. 31 is a plan view showing another example of the wiringlayout for an active shield in each of subdivided areas of the shieldarea;

[0041]FIG. 32 is a diagram showing an example of the layout of wiringlines and detectors, both constituting a shield system, in asemiconductor device according to an eleventh embodiment of the presentinvention;

[0042]FIG. 33 is a block diagram which illustrates an example of ashield system in a semiconductor device according to a twelfthembodiment of the present invention;

[0043]FIG. 34 is a block diagram which illustrates a configurationexample of a shield system in a semiconductor device according to athirteenth embodiment of the present invention;

[0044]FIG. 35 is a block diagram which illustrates an example of ashield system in a semiconductor device according to a fourteenthembodiment of the present invention;

[0045]FIG. 36 is a block diagram which illustrates an example of ashield system in a semiconductor device according to a fifteenthembodiment of the present invention;

[0046]FIG. 37 is a plan view showing an example of wiring for shieldingin a semiconductor device according to a sixteenth embodiment of thepresent invention;

[0047]FIG. 38 is a diagram showing an example of subdivision of a shieldarea;

[0048]FIG. 39 is a diagram showing another example of subdivision of ashield area; and

[0049]FIG. 40 is an enlarged plan view of a principal portion of asemiconductor chip which constitutes an IC card according to anineteenth embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0050] In the following specification, various embodiments will bedescribed, in which the subject matter of the invention may be dividedlyinto plural sections or embodiments where required for the sake ofconvenience; however, unless otherwise mentioned, it is to be understoodthat they are not unrelated to each other, but one is in the relation ofa modification or detailed or supplementary explanation of part or thewhole of the other.

[0051] When reference is made, for example, to the number of elements(including the number of pieces, numerical value, quantity, and range)in the following description of the embodiments, no limitation is madeto the specified number, but numbers above and below the specifiednumber will do unless otherwise specified, except for the case where alimitation is clearly directed to the specified number.

[0052] In the following description of the embodiments, moreover, itgoes without saying that their components (including constituent steps)are not always essential unless otherwise mentioned, except for the casewhere they are clearly considered essential.

[0053] Likewise, in the following description of the embodiments, it isto be understood that when reference is made to the shape or positionalrelation of a component, those characteristics substantially similar orclosely similar thereto are also included unless otherwise mentioned,except for the case where the answer is clearly negative. This is alsotrue of the foregoing numerical value and range.

[0054] In all of the drawings, portions having the same functions areidentified by like reference numerals, and repeated explanations thereofwill be omitted.

[0055] In the drawings, even plan views may be hatched to make themeasier to understand. Further, in the following description of theembodiments, a MIS•FET (Metal Insulator Semiconductor Field EffectTransistor) which typifies field effect transistors is abbreviated MIS,a

[0056] p-channel type MIS•FET is abbreviated pMIS, and an n-channelMIS•FET is abbreviated nMIS.

[0057] Various embodiments of the present invention will be described indetail hereinunder with reference to the accompanying drawings.

[0058] (First Embodiment)

[0059]FIG. 1 is a plan view of the whole of an IC card (a semiconductordevice) according to a first embodiment of the present invention, andFIG. 2 is a sectional view taken on line X1-X1 in FIG. 1.

[0060] The IC card 1 is of the type used as an information storagemedium in various fields, including finance, distribution, medical care,traffic, transportation, or education, such as electronic money, creditcard, portable telephone, chargeable satellite broadcast receiver,identification card, license, insurance policy, electronic medicalsheet, and electronic railroad ticket. The card body 1S of the IC card 1is constituted by a plastic sheet which is rectangular as seen in planview, for example. The length and width of the card body 1S are, forexample, 85.47 to 85.72×53.92 to 54.03 cm, and the thickness thereof is,for example, 0.68 to 1.84 mm.

[0061] In part of a main surface of the card body 1S there is providedan information storage area IMA which is generally quadrangular as seenin plan view. A groove 2 is formed in the information storage area IMAof the card body 1S, and a package 4 which incorporates a semiconductorchip (hereinafter referred to simply as “chip”) 3 is mounted therein inan embedded manner. The length and width of the information storage areaIMA are, for example, 11.4×12.6 cm.

[0062] The chip 3 is mounted on a package substrate 4 a in such a mannerthat the main surface (a device-forming surface) thereof faces thebottom of the groove 2, and the back side thereof is bonded to thepackage substrate 4 a. On the main surface of the chip 3 there is anintegrated circuit constituted by a logic circuit group 3 b, including,for example, memory circuits 3 a (see FIG. 18, for example), and a CPU(Central Processing Unit) for controlling the operation of the memorycircuits. The memory circuits 3 a are constituted, for example, by agroup of such memory elements (first elements) as non-volatile memoryelements and/or RAM (Random Access Memory), e.g., EEPROM (ElectricErasable Programmable Read Only Memory), flash memory, and mask ROM.

[0063] Electrodes of the integrated circuit formed on the chip 3 aredrawn out by external terminals BP, such as bonding pads. The bondingpads are electrically connected through bonding wires 4 b to landsformed on a main surface of the package substrate 4 a. The chip 3 andthe bonding wires 4 b are sealed with sealing resin 4 c, e.g., epoxyresin. The back side of the package substrate 4 a, i.e., the sideopposite to the mounting surface of the chip 3, faces a surface of theIC card 1. On the back side of the package substrate 4 a, pluralelectrodes are formed which are electrically connected to electrodesformed on the main surface of the package substrate 4 a. Through theseelectrodes, it is possible to supply data to the chip 3 from theexterior and receive data from the chip.

[0064] The method used for mounting the chip 3 is not limited to the oneillustrated in FIG. 2. For example, a face-down bonding method may beadopted, as shown in FIG. 3. According to this method, bump electrodes 4d are formed on the external terminals BP, and with the main surface(device-forming surface) of the chip 3 arranged to face the packagesubstrate 4 a, the chip 3 is mounted onto the package substrate 4 athrough the bump electrodes 4 d that have been formed on the mainsurface of the chip 3. The integrated circuit of the chip 3 iselectrically connected through the external terminals BP and bumpelectrodes 4 d to wiring formed on the package substrate 4 a.

[0065]FIG. 4 is a plan view of a top wiring layer formed on the mainsurface side of the chip 3 that is shown in FIG. 2 or FIG. 3. Asemiconductor substrate (simply “substrate” hereinafter) 3S, whichconstitutes the chip 3, is constituted by a small piece of a singlecrystal of p-type silicon (Si) which is square as seen in plan view, forexample. In this first embodiment, as shown in FIG. 4, bonding pads BPAto BPF are arranged near an outer periphery of the chip 3, of which BPAand BPB are patterned integrally with wiring lines 5A and 5B for thesupply voltage and are connected electrically thereto. The bonding padBPC is a terminal for input of a clock signal for example. The bondingpad BPD is a terminal, used for input of a predetermined control signal,for example. Further, the bonding pads BPE and BPF are terminals fortransmission and reception of input and output signals.

[0066] The wiring lines 5A and 5B for the supply voltage are arranged soas to cover the main surface of the chip 3. That is, the wiring lines 5Aand 5B are arranged so as to cover the integrated circuit (memorycircuits 3 a and logic circuit group 3 b). The wiring line 5A is usedfor the supply of a supply voltage (GND, e.g., 0V) on a low potentialside to the integrated circuit formed on the chip 3. The wiring line 5Bis used for the supply of a supply voltage (VCC, e.g., 1.8V, 3.0V, 5.0V)on a high potential side to the integrated circuit formed on the chip 3.The wiring lines 5A and 5B are formed in the shape of comb teeth as seenin plan view and the respective teeth are arranged so as to mesh witheach other in the same wiring layer. Both wiring lines 5A and 5Bthdisposed adjacent to each other are arranged so that the spacingbetween them is as narrow as possible. That is, the elements on the mainsurface of the chip 3 are covered closely without any gap by both wiringlines 5A and 5B. Consequently, even if an attempt is made to apply aneedle to a signal line which underlies the wiring lines 5A and 5B forthe purpose of analyzing information stored in the chip 3, it cannot bedone because access is obstructed by both wiring lines 5A and 5B.Observing from the exterior the signal lines and elements that underliethe wiring lines 5A and 5B is very difficult because all elements areobstructed by both wiring lines 5A and 5B. That is, the wiring lines 5Aand 5B function as a shield for protecting information. Therefore, inthe structure of this first embodiment, for analyzing information storedin the chip 3, it is necessary to remove the wiring lines 5A and 5Bwhich carry the supply voltage. However, since both wiring lines 5A and5B operate to supply an operating voltage to the integrated circuitformed on the chip 3, if they are removed, the supply voltage is nolonger fed to the integrated circuit, with the result that theintegrated circuit does not operate, and it is impossible to analyze theinformation stored in the chip 3. Thus, it is possible to improve thesecurity of information carried in the IC card 1.

[0067]FIG. 5 is a plan view of a principal portion of an element areaformed on the main surface of the chip 3 shown in FIG. 4, and FIG. 6 isa sectional view taken on line X2-X2 in FIG. 5. On a main surface sideof the substrate 3S, a field insulating film 6 is formed in an isolationregion. The field insulating film 6 is formed of a silicon oxide (e.g.,SiO₂) by a selective oxidation (LOCOS: Local Oxidation of Silicon)method, for example. The field insulating film 6 may be replaced by agrooved isolation region (SGI: Shallow Groove Isolation). The groovedisolation region is formed by embedding an insulating film, such as asilicon oxide film, into a groove formed in the main surface of thesubstrate 3S. An active region is formed in the area surrounded with thefield insulating film 6 and the grooved isolation region.

[0068] Further, n-well and p-well PWL are formed to a predetermineddepth from the main surface of the substrate 3S. For example, phosphorus(P) or arsenic (As) is contained in the n-well, while boron (B) or borondifluoride (BF₂) is contained in the p-well. Within the area of then-well and in the active region surrounded with the field insulatingfilm 6 there are disposed a pMIS (second element) Qp and a well powersupply region NWP, which are isolated from each other through the fieldinsulating film 6.

[0069] The pMIS Qp comprises a p-type semiconductor region 7 a for thesource, a p-type semiconductor region 7 b for the drain, a gateinsulating film 8, and a gate electrode 9. For example, boron (B) iscontained in the p-type semiconductor regions 7 a and 7 b. The gateinsulating film 8 is formed of a silicon oxide, for example, providedthe material of the gate insulating film 8 is not limited thereto, butany of various other materials may be used. For example, the gateinsulating film 8 may be a silicon oxynitride film(SiON). That is, astructure may be adopted wherein nitrogen is segregated in an interfacebetween the gate insulating film 8 and the substrate 3S. The siliconoxynitride film is more effective than the silicon oxide film insuppressing the generation of an interface state in the film or indiminishing an electron trap, so that it is possible to improve the hotcarrier resistance of the gate insulating film 8 and improve thedielectric strength. Besides, it is more difficult for impurities topenetrate through the silicon oxynitride film than through the siliconoxide film, so that, by using the silicon oxynitride film, it ispossible to suppress a variation of the threshold voltage caused bydiffusion of an impurity contained in the gate electrode material towardthe substrate 3S. The silicon oxynitride film can be formed, forexample, by heat-treating the substrate 3S in a nitrogen gas-containingatmosphere, such as NO, NO₂, or NH₃. Also by heat-treating the substrate3S in the nitrogen gas-containing atmosphere after formation of the gateinsulating film 8 of a silicon oxide on the surface of the substrate 3Sand by subsequently segregating nitrogen in the interface between thegate insulating film 8 and the substrate 3S, the same effect can beobtained as indicated above. The gate electrode 9 is formed of a lowresistance polycrystalline silicon, for example, although no limitationis made thereto, but any of various other materials may be used. Forexample, a so-called polycide gate electrode structure may be adoptedwherein a silicide layer, such as cobalt silicide (CoSi_(x)) layer, isformed on a low resistance polycrystalline silicon film, or a so-calledpolymetal gate electrode structure wherein a metal film such as tungstenfilm is formed on a low resistance polycrystalline silicon film, througha barrier metal layer, such as a tungsten nitride (WN) layer. The wellpower supply region NWP is used for applying a back bias voltage to then-well and is formed by the presence of, for example, phosphorus orarsenic on top of the n-well at a higher concentration than in then-well itself.

[0070] Within the area of the p-well PWL, and in the active regionsurrounded with the field insulating film 6, there are an nMIS (secondelement) Qn and a well power supply region PWP, which are isolated fromeach other through the field insulating film 6.

[0071] The nMIS Qn comprises an n-type semiconductor region 10 a for thesource, an n-type semiconductor region 10 b for the drain, a gateinsulating film 8, and a gate electrode 9. For example, phosphorus orarsenic is contained in the n-type semiconductor regions 10 a and 10 b.As to the structure of the gate insulating film 8 and gate electrode 9in the nMIS Qn, an explanation thereof will be omitted because it is thesame as that described above in connection with the pMIS Qp. The gateelectrode 9 of the pMIS Qp and that of the nMIS Qn are integrallypatterned and are connected electrically with each other. The gateelectrode 9 serves as an input of a CMIS inverter circuit which isconstituted by both a pMIS Qp and a nMIS Qn. The well power supplyregion PWO is used for applying a back bias voltage to the p-well PWIand is formed by the presence of, for example, boron or boron difluorideon top of the p-well PWL at a higher concentration than in the p-wellPWL itself.

[0072] The integrated circuit (memory circuits 3 a and logic circuitgroup 3 b) is constituted by the pMIS Qp and/or the nMIS Qn. Aninterlayer insulating film constituted by a silicon oxide film, forexample, is deposited on the main surface of the substrate 3S.First-layer wirings 12 a to 12 f each constituted by a metallic film,such as an aluminum (Al) or aluminum alloy film, are formed on theinterlayer insulating film 11 a. The first-layer wiring 12 a iselectrically connected to the gate electrode 9 through a plug disposedwithin a contact hole CNT. The first-layer wiring 12 b is electricallyconnected to both p-type semiconductor region 7 b and n-typesemiconductor region 10 b for the drain of the pMIS Qp and the nMIS Qn,each through a plug PL1 that is disposed within a contact hole CNT. Thatis, the first-layer wiring 12 b serves as an output of a CMIS invertercircuit. The first-layer wiring 12 c is electrically connected to thep-type semiconductor region 7 a of the pMIS Qp through a plug that isdisposed within a contact hole CNT. The first-layer wiring 12 d iselectrically connected to the well power supply region NWP through aplug that is disposed within a contact hole CNT. The first-layer wiring12 e is electrically connected to the n-type semiconductor region 10 aof the nMIS Qn through a plug PL1 that is disposed within a contact holeCNT. The first-layer wiring 12 f is electrically connected to the wellpower supply region PWP through a plug PL1 that is disposed within acontact hole CNT. The plug PL1 is constituted, for example, by ametallic film, such as aluminum, aluminum alloy, or a tungsten film.

[0073] An interlayer insulating film 11 b constituted by a silicon oxidefilm, for example, is deposited on the interlayer insulating film 11 ato cover the first-layer wirings 12 a to 12 f. Second-layer wirings 13 ato 13 d, each constituted by a metallic film, such as, for example,aluminum or aluminum alloy film, are formed on the interlayer insulatingfilm 11 b. The second-layer wiring 13 a is electrically connected to thefirst-layer wiring 12 e through a plug PL2 that is disposed within athrough hole TH1 formed in the interlayer insulating film 11 b. Thesecond-layer wiring 13 b is electrically connected to the first-layerwiring line 12 b through a plug PL2 that is disposed within a throughhole TH1 formed in the interlayer insulating film 11 b. The second-layerwiring 13 c is electrically connected to the first-layer wiring 12 fthrough a plug PL2 that is disposed within a through hole TH1 formed inthe interlayer insulating film 11 b.

[0074] Further, an interlayer insulating film 11 c, constituted by asilicon oxide film, for example, is formed on the interlayer insulatingfilm 11 b to cover the second-layer wirings 13 a to 13 d. A third-layerwiring 14 constituted by a metallic film, such as, for example, analuminum or aluminum alloy film, is formed on the interlayer insulatingfilm 11 c. The wiring lines 5A and 5B for the supply voltage are formedby the third-layer wiring 14. In FIG. 6, there is illustrated the wiringline 5B for the supply voltage on a low potential side. The third-layerwiring 14 is electrically connected to the second-layer wirings 13 a and13 c, each through a plug PL3 that is disposed within a through holeTH2. That is, the wiring line 5A for the supply voltage on a lowpotential side is electrically connected to the n-type semiconductorregion 10 a for the source of the nMIS Qn and also to the power supplyregion PWP. The wiring line 5B for the supply voltage on a highpotential side is electrically connected to the p-type semiconductorregion 7 a for the source of the pMIS Qp and also to the power supplyregion NWP. Further, a surface protecting film 15 is deposited on theinterlayer insulating film 11 c. The surface protecting film 15 isformed by depositing an insulating film 15 b made of a polyimide resin,for example, onto an insulating film 15 a made of a silicon nitride filmwhich is formed by a plasma CVD (Chemical Vapor Deposition) method, forexample. The wiring lines 5A and 5B may each be constituted so as tofeed a supply voltage to the MIS•FET well region located near a lowerportion thereof. In this case, if portions of the wiring lines 5A and 5Bare cut or removed, the supply voltage is not fed to the integratedcircuits 3 a and 3 b located near lower positions of the removedportions, or of the portions of the wiring lines 5A and 5B which havebecome disconnected electrically from the bonding pads BPA and BPB, sothat the integrated circuits fail to operate, and it becomes impossibleto analyze information stored in the chip 3.

[0075] (Second Embodiment)

[0076]FIG. 7 is a plan view of a chip 3 which constitutes an IC cardaccording to a second embodiment of the present invention.

[0077] In this second embodiment, as shown in FIG. 7, wiring lines 5Aand 5B for the supply voltage are substantially in the shape of a ladderor grid, as seen in plan view. More specifically, the wiring lines 5Aand 5B each comprise two wiring portions extending in parallel with eachother vertically, as seen in FIG. 7, and plural wiring portionsextending perpendicularly to the two wiring portions and arranged atpredetermined intervals vertically, as seen in FIG. 7, both wiringportions being connected together at their intersecting points.

[0078] However, in this second embodiment, the wiring lines 5A and 5Bare formed respectively in different wiring layers with an interlayerinsulating film being disposed therebetween. In the illustrated example,the wiring line 5B for the supply voltage on a high potential sideoverlies the wiring line 5A for the supply voltage on a low potentialside. The planar positions of the wiring lines 5A and 5B are shiftedrelative to each other so that the wiring line 5B is partially locatedin gaps of the wiring line 5A. That is, also in this second embodiment,elements on the main surface of the chip 3 are covered closely withoutleaving any gap by the wiring lines 5A and 5B. Therefore, even if anattempt is made to apply a needle to a signal line which underlies thewiring lines 5A and 5B for the purpose of analyzing information storedin the chip 3, it cannot be done because access is obstructed by bothwiring lines 5A and 5B. Besides, observing from the exterior such signallines and elements as underlie the wiring lines 5A and 5B is verydifficult because all elements are obstructed by both wiring lines 5Aand 5B. Thus, also in this second embodiment, for analyzing informationstored in the chip 3, it is necessary to remove the wiring lines 5A and5B for the supply voltage. However, if both wiring lines 5A and 5B areremoved, the integrated circuit does not operate, and it is impossibleto analyze information stored in the chip 3 for the same reason as thatstated in connection with the previous first embodiment. Thus, it ispossible to improve the security of information stored in the IC card.

[0079] (Third Embodiment)

[0080]FIG. 8 is a plan view of a chip 3 which constitutes an IC cardaccording to a third embodiment of the present invention.

[0081] In this third embodiment, as shown in FIG. 8, wiring lines 5A and5B for the supply voltage are substantially in the shape of a lattice asseen in plan view. More specifically, the wiring lines 5A and 5B eachcomprise plural wiring portions extending vertically, as seen in FIG. 8,in parallel with one another and plural wiring portions extendingperpendicularly thereto, both wiring portions being connected togetherat their intersecting points.

[0082] Also, in this third embodiment, the wiring lines 5A and 5B areformed respectively in different wiring layers. Also, in the illustratedexample, the wiring lines 5B for the supply voltage on a high potentialside overlie the wiring lines 5A for the supply voltage on a lowpotential side. Further, also in this third embodiment, the planarpositions of the wiring lines 5A and 5B for the supply voltage areshifted relative to each other so that the wiring line 5B is partiallydisposed in gaps of the wiring line 5A. With this arrangement in thisthird embodiment, it is also possible to obtain the same effect as thatobtained in the first and second embodiments.

[0083] (Fourth Embodiment)

[0084]FIG. 9 is a plan view of a chip 3 which constitutes an IC cardaccording to a fourth embodiment of the present invention, and FIG. 10is a sectional view taken on line X3-X3 in FIG. 9.

[0085] In this fourth embodiment, as shown in FIG. 9, a wiring line 5Afor the supply voltage on a low potential side is solid wiring. That is,the wiring line 5A is formed in a quadrangular shape, as seen in planview, so as to cover the greater part of a main surface of a chip 3. Ofcourse, a wiring line 5B for the supply voltage on a high potential sidemay be made as a solid wiring as well. In this embodiment, the wiringline 5B for the supply voltage on a high potential side is disposed in awiring layer which underlies the wiring line 5A for supply voltage on alow potential side. Since through holes TH3 for pulling down the wiringline 5A to the underlying layer are to be formed, the wiring line 5B isnot made as a solid wiring, but is formed as an ordinary band-like orwide wiring line.

[0086] Also, in this fourth embodiment, which is constructed asdescribed above, the same effect can be obtained as that obtained in thefirst and second embodiments.

[0087] (Fifth Embodiment)

[0088]FIG. 11 is a plan view showing a chip 3 which constitutes an ICcard according to a fifth embodiment of the present invention. Pluralcircuit blocks 16A to 16D are arranged on a main surface of the chip 3.In the circuit block 16A, there is a RAM (Random Access Memory) such as,for example, a DRAM (Dynamic Random Access Memory), a SRAM (StaticRandom Access Memory), a FRAM (Ferroelectric Random Access Memory). Inthe circuit block 16B, there is an EEPROM (Electric ErasableProgrammable Read Only Memory), for example. Various items ofinformation, such as those related to finance, distribution, medicalcare, traffic, or transportation, are stored in the circuit block 16B.In the circuit block 16C, there is a CPU (Central Processing Unit), forexample. The operation of the integrated circuit within the chip 3 iscontrolled by the circuit block 16C. In the circuit block 16D, there isa ROM (Read Only Memory), for example. Information items necessary foroperation of the integrated circuit are stored in the circuit block 16D.A wiring region 17 is disposed among the circuit blocks 16A to 16D. Inthe wiring region 17, there are arranged such signal lines as bus lines18 a, 18 b and control signal lines 18 c to 18 e. The bus lines 18 a and18 b are each constituted by a group of plural signal lines juxtaposedat approximately equal intervals.

[0089] In this fifth embodiment, the wiring lines 5A and 5B for thesupply voltage are arranged so as to partially cover a broken-line areaLA in the wiring region 17. That is, both wiring lines 5A and 5B arearranged so as to partially cover signal lines used for the analysis ofinformation, such as bus lines 18 a, 18 b and control signal lines 18 cto 18 e.

[0090] Also, in this fifth embodiment, as is the case with the previousfirst to fourth embodiments, the wiring lines 5A and 5B for the supplyvoltage must be removed to obtain access for analyzing information. Ifboth wiring lines 5A and 5B are removed, however, for the reason statedabove, the integrated circuit does not operate, and it is impossible toanalyze the information stored in the chip. Thus, it is possible toimprove the security of information stored in the IC card 1.

[0091] In this fifth embodiment, moreover, the wiring lines for thesupply voltage, which function as a shield, may be disposed partially,and the other area may be used as a power supply wiring area or signalwiring area for the other circuit blocks 16A to 16D. Thus, even if thereare wiring lines 5A and 5B for the supply voltage which function as ashield, it is possible to ensure the overall wiring layout freedom.

[0092] (Sixth Embodiment)

[0093]FIG. 12 is a plan view of a chip 3 which constitutes an IC cardaccording to a sixth embodiment of the present invention. On a mainsurface of the chip 3, plural circuit cells 19 are arranged side by sidewithout any gap, and they are disposed regularly in both vertical andtransverse directions, as seen in FIG. 12. Plural elements are arrangedin each of the circuit cells 19.

[0094] Although a description has been given relative to the first tofifth embodiments concerning a technique for protecting informationstored in the chip 3 on the assumption that all of the wiring lines 5Aand 5B for the supply voltage, which function as a shield, are removed,it is possible to adopt another method wherein the wiring lines 5A and5B are partially removed using an energy beam, such as a FIB (FocusedIon Beam), for example, after which the analysis of information isperformed. In this sixth embodiment, for preventing the analysis ofinformation based on such partial removal of the power supply lines, forexample, plural processing detector circuits 20 are provided on a mainsurface of the chip 3.

[0095] With provision of the processing detector circuits 20, once thewiring lines 5A and 5B for the supply voltage in the previous first tofifth embodiments, or a specific wiring line formed on the chip 3, issubjected to processing (complete or partial cutting), the processing isdetected, and the integrated circuit in the chip 3 is reset so that itis made unable to operate, thereby preventing the analysis ofinformation. With such processing detector circuits 20, it is possibleto prevent the analysis of information stored in the IC card 1, and,hence, it is possible to improve the security of information stored onthe card.

[0096] In this sixth embodiment, plural processing detector circuits 20are dispersed irregularly within the main surface of the chip 3, wherebyit is possible to make it difficult to identify the positions of theprocessing detector circuits 20 in the chip 3. In this regard, foranalyzing information stored in the chip 3, it is conceivable that,after destroying the processing detector circuits 20, the foregoingwiring lines which function as a shield can be removed, followed byanalysis of information stored in the chip 3. Therefore, if pluralprocessing detector circuits 20 are arranged in an irregularly dispersedfashion, it becomes difficult to destroy all of the processing detectorcircuits, and, hence, it is possible to make the analysis of informationdifficult. As a result, it becomes possible to further improve thesecurity of information stored in the chip 3. Once the wiring lines 5Aand 5B for the supply voltage are subjected to processing (complete orpartial cutting), the processing detector circuits 20 are able to detecta change in potential (or resistance) of the wiring lines 5A and 5B.That is, the processing detector circuits 20 are used for the detectionof tampering with the wiring lines 5A and 5B.

[0097]FIG. 13 shows an example of a circuit diagram representing each ofthe processing detector circuits 20. According to the illustratedcircuit configuration, even if one of the wiring line 5A for the supplyvoltage (GND) on a low potential side and the wiring line 5B for thesupply voltage (VCC) on a high potential side is subjected toprocessing, the processing can be detected by one processing detectorcircuit 20.

[0098] The processing detector circuit 20 has high resistors R1 and R2,nMIS Qn1, pMIS Qp1, an inverter circuit INV1, a nor circuit NR1, and aninverter circuit INV2. The processing detector circuit 20 is constitutedby the elements arranged within each circuit cell 19, and a circuit isformed such that the elements are interconnected by wiring lines whichunderlie the wiring layer of the wiring lines 5A and 5B for the supplyvoltage. The wiring lines 5A and 5B for the supply voltage serve asinputs of the processing detector circuit 20. Supply voltages VCC1 andGND1, which serve as drive voltages for the processing detector circuit20, should be fed along a route different from the wiring lines 5A and5B, or else, if any of the wiring lines 5A and 5B is cut off, theprocessing detector circuit 20 itself will fail to operate and will nolonger function as a detector circuit. In the illustrated example, thesupply voltage GND1 is equal (for example, 0V or so) to the voltageapplied to the wiring line 5A for the supply voltage on the lowpotential side, and the supply voltage VCC1 is equal (for example, 1.8V,3.0V, or 5.0V or so) to the voltage applied to the wiring line 5B forthe supply voltage on the high potential side.

[0099] A sleep terminal SLP is electrically connected to a gateelectrode of the nMIS Qn1, and it is also connected to a gate electrodeof the pMIS Qp1 through an inverter circuit INV3. If a voltage of “High(simply H herenafter)” level is applied to the sleep terminal SLP, boththe nMIS Qn1 and the pMIS Qn1 turn ON, and the processing detectorcircuit 20 performs its normal operation. On the other hand, if avoltage of “Low (simply L hereinafter) level is applied to the sleepterminal SLP, both the nMIS Qn1 and the pMIS Qp turn OFF, and theprocessing detector circuit 20 assumes a sleep state. The referencemarks N1 to N4 denote nodes and the reference mark OUT denotes an outputof the processing detector circuit 20.

[0100]FIG. 14 shows potentials of the nodes N1 to N4 and the output OUTin various operation modes of each processing detector circuit 20 shownin FIG. 13. Mode M1 is a normal operation mode of the processingdetector circuit 20, i.e., a processing-free state of the wiring lines5A and 5B. In this case, the nodes N1, N2, and N3 assume L, H, and Llevels, respectively, so that the output node N4 of NOR circuit NR1becomes H, and after inversion in the inverter circuit INV2, a signal ofL level is provided at the output OUT of the processing detector circuit20. In this case, the integrated circuit in the chip 3 is not reset.

[0101] In mode M2, the wiring line 5B on the high potential side is cutoff, although the wiring line 5A on the low potential side is not cutoff. In this case, the nodes N2 and N3 assume L and H levels,respectively, so that the output node N4 of the NOR circuit NR1 becomesL, and after inversion in the inverter circuit INV 2, H is provided atthe output OUT of the processing detector circuit 20. As a result, theintegrated circuit in the chip 3 is reset and does not operate, thusmaking it possible to prevent the analysis of information. Further, inmode M3, the wiring line 5A on the low potential side is cut offalthough the wiring line 5B on a high potential side is not cut off. Inthis case, the node N1 becomes H and the output node N4 of the NORcircuit NR1 becomes L, so that, after inversion in the inverter circuitINV2, a signal of H level is provided at the output OUT of theprocessing detector circuit 20. As a result, as in the case of mode M2,the integrated circuit of the chip 3 is reset and does not operate,thereby making the analysis of information impossible.

[0102]FIG. 15 shows an example of the layout of the wirings 5A and 5Bfor the supply voltage, which function as a shield, and FIG. 16 is asectional view taken on line X4-X4 in FIG. 15. Although these figuresshow an example of a processing detector circuit 20 using either thewiring line 5A or 5B as an input, it is possible to use a processingdetector circuit 20 as referred to above, which uses both wiring lines5A and 5B as inputs.

[0103] In this sixth embodiment, each of the wiring lines 5A and 5B isconstituted by a respective wiring line which meanders so as to coverunderlying wiring lines 18. That is, each of the wiring lines 5A and 5Bis constituted as a single continuous path so that, when cut off, thecut-off wiring portions are completely isolated from each other.Further, though the invention is not specially so limited, processingdetector circuits 20 are electrically connected to terminal ends of suchwiring lines 5A and 5B. If the wiring lines 5A and 5B are arranged in aframe- or lattice-like layout, as described previously, even if they arecut off partially, it is possible to feed supply voltage through theother wiring portions, and, therefore, the input potential of eachprocessing detector circuit 20 becomes constant, with the result that,even when the wirings 5A and 5B are subjected to processing, theprocessing cannot be detected. On the other hand, in this sixthembodiment, the wirings 5A and 5B are each constituted by a wiring linedisposed as a single continuous path. In analyzing information,therefore, if part of the wiring lines 5A and 5B is cut off with anenergy beam, such as a FIB, it becomes no longer possible to apply asupply voltage to an input of each processing detector circuit 20, andthe input potential of the circuit 20 changes. As a result, it becomespossible to carry out a processing detection by the processing detectorcircuit 20 as described above, and it is possible to prevent theanalysis of information stored in the chip 3.

[0104] In the illustrated example being considered, the wiring lines 5Aand 5B are provided in different wiring layers with an interlayerinsulating film disposed therebetween, though the invention is notspecially limited. That is, the wiring line 5A overlies the wiring line5B. Both wiring lines 5A and 5B are arranged so as to intersect witheach other, as seen in plan view. More specifically, since theunderlying wiring lines 18 are covered in a gap-free manner with thewirings 5A and 5B for the supply voltage, even if an attempt is made toapply a needle to the wiring lines 18 which underlie the wiring lines 5Aand 5B for the purpose of analyzing information stored in the chip 3,this will not be successful because the needle is obstructed by bothwiring lines 5A and 5B. Further, observing from the exterior the signallines and elements which underlie the wiring lines 5A and 5B for supplyvoltage is extremely difficult because they are obstructed by bothwiring lines 5A and 5B. Therefore, also in the case of this sixthembodiment, it is necessary to process both of the wiring lines 5A and5B for the supply voltage in case of analyzing information stored in thechip 3. But if such is done, the processing is detected by theprocessing detector circuits 20, with the result that the integratedcircuit fails to operate, and it is impossible to analyze informationstored in the chip 3. Thus, it is possible to improve the security ofinformation stored in the IC card 1. As an example of the wiring lines18, mention may be made of a desired signal line, such as a bus line(including control bus, data bus, or address bus) or control line.

[0105] The underlying processing detector circuits 20 may be coveredwith the meandering wiring lines 5A and 5B. For analyzing informationstored in the chip 3, it is also possible to adopt a method involvingthe destroying of the processing detector circuits 20 and subsequentremoval of wiring lines 5A, 5B to effect analysis of information.However, if the processing detector circuits 20 are covered with thewiring lines 5A and 5B, as described above, it is necessary to cut offthe wiring lines 5A and 5B for destroying the processing detectorcircuits 20, that is, it is possible to detect processing of the wiringlines 5A and 5B before destruction of the processing detector circuits20, and, hence, it is possible to prevent the analysis of information.

[0106] Such a continuous line stroke construction of the wiring lines 5Aand 5B is also applicable to the case where the processing detectorcircuits 20 are not provided. More specifically, if the greater part ofthe main surface of the chip 3, or only the wiring region, is coveredwith such continuous wiring lines 5A and 5B as illustrated in FIG. 16,even if a part of the wiring lines 5A and 5B is cut off, there will beno feed of supply voltage to the integrated circuit in the chip 3; and,hence, the integrated circuit fails to operate, whereby it is possibleto prevent the analysis of information.

[0107] Both wiring lines 5A and 5B may be constituted so as to haverespective planar patterns that are different from each other, wherebyit is possible to make the analysis of information difficult.

[0108] Although in this embodiment the wiring lines 5A and 5B areprovided in different wiring layers, both wiring lines may be providedin the same wiring layer, as shown in FIG. 40, whereby there is obtainedthe same effect as that obtained in this embodiment.

[0109] Moreover, as shown in FIG. 40, by constructing the wiring lines5A and 5B so as to have respective planar patterns that are differentfrom each other, it is possible to make the analysis of information moredifficult.

[0110] The same wiring layer for both wiring lines 5A and 5B, as shownin FIG. 40, may be provided in a plural number and plural wiring layersmay be laminated together. That is, the wiring lines 5A and 5B shown inFIG. 40 may be provided in each of plural wiring layers. In this case,by making the planar patterns of both of the wiring lines 5A and 5B inone wiring layer different from that in another wiring layer, it ispossible to make the analysis of information more difficult.

[0111] Moreover, by laminating the wiring layer having the planarpattern shown in FIG. 15 and the wiring layer having the planar patternshown in FIG. 40 to each other, it is possible to make the analysis ofinformation even more difficult. Further, the wiring patterns of wirings5A and 5B shown in FIG. 40 may be provided in a wiring layer that isformed between the wiring layer of wiring line 5B and that of wiringline 5B shown in FIG. 15. In this case, by forming the wiring pattern ofwiring line 5B shown in FIG. 15, that of the wiring line 5A shown inFIG. 15, and the wiring patterns of wiring lines 5A and 5B, with use ofplanar patterns that are different from one another, it is possible tomake the analysis of information that much more difficult.

[0112] (Seventh Embodiment)

[0113] In the sixth embodiment, the route of the wiring for supplyvoltage functioning as a processing detection wiring and the route ofthe wiring for the supply voltage to feed a drive voltage to eachprocessing detector circuit are provided separate from each other. Butin this seventh embodiment, as shown in FIG. 17, the supply voltages GNDand VCC of the wiring lines 5A and 5B, which function as processingdetection lines in one processing detector circuit (20 a to 20 d), andthe supply voltages GND1 and VCC1 which serve as drive voltages for theother processing detector circuits 20 (20 a to 20 d), are fed through anintegral supply route. More specifically, wiring lines 5A and 5B forprocessing detection input in one processing detector circuit 20 areprovided as wiring lines 5A and 5B for the supply of drive voltage inanother processing detector circuit 20. In the illustrated example, theprocessing detector circuits 20 a to 20 d are arranged so as to form aloop.

[0114] In an attempt to analyze information stored in the IC card 1, itis possible to adopt a method wherein the supply voltages GND1 and VCC1are cut off (or are prevented from being supplied) so as to preventoperation of the processing detector circuits 20, and, thereafter, thewiring lines 5A and 5B are cut off to analyze the information on thecard. To prevent use of such a method, this seventh embodiment adopts aconstruction wherein, if the wiring lines for feeding the supplyvoltages GND1 and VCC1 in one processing detector circuit 20 are cut off(or prevented from being supplied), the cutting is detected by anotherprocessing detector circuit 20. For example, if the wiring lines for thesupply of the supply voltages GND1 and VCC1, which serve as the drivevoltage for the processing detector circuit 20 b, are cut off, theprocessing detector circuit 20 a detects the cutting and operates toprevent operation of the integrated circuit in the chip 3. Thus, theanalysis of information can be prevented, and it is possible to furtherimprove the security of the IC card 1.

[0115] Also in this seventh embodiment, the wiring lines 5A and 5B maybe configured so as to meander, as shown in FIG. 16, to cover theunderlying processing detector circuits 20. With this construction, ifan attempt is made to destroy the processing detector circuits 20, thesame circuits detect it and prevent operation of the integrated circuitin the chip 2, whereby the analysis of information can be prevented.

[0116] (Eighth Embodiment)

[0117] In this eighth embodiment, a description will be given of anexample in which the supply voltage wiring lines having a shieldingfunction and wiring lines for providing an active shield are arranged indifferent planar positions. As will be described later, the activeshield is a shield of the type described in connection with the sixthand seventh embodiments.

[0118]FIG. 19 is a plan view of a chip 3 which constitutes asemiconductor device according to an eighth embodiment of the presentinvention. The wiring lines 5A and 5 b shown in FIG. 19 correspond tothe power supply wiring lines having a shielding function, as has beenexplained in connection with the first to fifth embodiments. In FIG. 19,as is the case with the first embodiment, the wiring lines 5A and 5B areformed in the same layer (top wiring layer). However, the wiring lines5A and 5B may be formed in different layers, as provided in the secondembodiment. The wiring lines 5A and 5B may have a planar shape asdescribed in conjunction with the third and fourth embodiments.

[0119] In the arrangement of FIG. 19, the wiring lines 5A and 5B arearranged so as to mainly cover a part (upper side of the chip 3 in thesame figure) of a main surface of the chip 3 and are not arranged in anarea (second area) LA. In the same figure there is illustrated an areawherein signal lines used in the analysis of information, such as buslines 18 a, 18 b and control signal lines 18 c to 18 e, are arranged. Inthis eighth embodiment, wiring lines for providing an active shieldconstituted by the same wiring layer as that of the wiring lines 5A and5B are arranged in the area LA. That is, the integrated circuit(comprising memory circuits 3 a and a logic circuit group 3 b) iscovered with the supply voltage wiring lines 5A and 5B, that are formedin the area other than the area LA and have a shielding function, andalso with wiring lines for providing an active shield formed in the areaLA.

[0120] The wiring lines 5A and 5B, which have a shielding function, maybe constituted by the planar patterns of the wiring lines 5A and 5Bshown in connection with the first to fifth embodiments and pluralwiring layers, and the wiring lines for providing an active shield maybe constituted by the planar patterns of the wiring lines 5A and 5B foran active shield shown in connection with the sixth embodiment andplural wiring layers. That is, the wiring lines for the supply voltagehaving a shielding function may be constituted by a single wiring layeror plural wiring layers and the wiring lines for providing an activeshield may be constituted by a single wiring layer or plural wiringlayers. Further, the wiring lines having a shielding function and thewiring lines for providing an active shield each have at least one andthe same wiring layer, whereby the wiring lines can be arranged so as tocover the integrated circuit (memory circuits 3 a and a logic circuitgroup 3 b) with the same wiring layer, thus making the analysis ofinformation more difficult.

[0121] The active shield is a shield as described in connection with thesixth and seventh embodiments. That is, as described in connection withthe sixth embodiment, the active shield has a function such that, ifspecific wiring lines (wiring lines for an active shield) whichconstitute an active shield are processed (cut off completely orpartially), the cutting is detected and the integrated circuit in thechip 3 is reset so as to prevent operation of the integrated circuit,thereby preventing analysis of information on the card. Signal linesused for the analysis of information, such as bus lines 18 a, 18 b andcontrol signal lines 18 c to 18 e in the region LA, are protected by theactive shield system in question. According to this system, if wiringlines for the active shield are processed (cut off completely orpartially) with an FIB (Focused Ion Beam), for example, a potentialchange in the wiring lines for the active shield is detected and adetected signal is inputted to a control circuit which controls thewhole integrated circuit in the chip 3 to activate a reset signal in theintegrated circuit, i.e., to reset the integrated circuit. As a result,the integrated circuit in the chip 3 fails to operate, and it isimpossible to analyze information. The reset state indicates a state inwhich the chip does not operate, i.e., a locked state. However, what isimportant is to prevent operation of the integrated circuit in the chip3 when the wiring lines for the active shield are processed. It is notthat there is a limitation on the reset state of the IC card. Forexample, an improvement may be made such that, once the wiring lines foran active shied are processed, there is a shift in operation to a deadmode in which the integrated circuit in the chip 3 will never operate.As a specific example, a fuse circuit serving as an active shield systemwill be provided within the chip 3, and once the wiring lines for activeshield are processed, the fuse in the fuse circuit is cut offautomatically and the integrated circuit in the chip 3 is destroyed, sothat it will never be operable (this is also the case with otherembodiments with respect to reset).

[0122] The wiring lines for the active shield are arranged through aninterlayer insulating film in a layer which overlies the layer of signallines, such as bus lines 18 a, 18 b and control signal lines 18 c to 18e. That is, the wiring lines for the active shield are arranged in sucha position that processing (complete or partial cutting) becomesinevitable at the time of any attempt at analyzing information throughaccess to the signal lines. As a result, for analyzing informationthrough access to the signal lines, it is necessary to process thewiring lines for the active shield, whereby it is possible to make itmore difficult to analyze information in the IC card through access tothe signal lines. Thus, in this eighth embodiment, by arrangingdifferent types (or methods) of shields (the shield using the supplyvoltage wiring lines 5A, 5B and the wiring lines for active shield) inthe same wiring layer, it is possible to make decryption, orcodebreaking, of the shield system difficult, and it is also possible tomake efforts at cancellation or causing failure of the shield system tooperate more difficult, so that the analysis of information stored inthe IC card can be made more difficult. Moreover, even if various types(or methods) of shield systems are formed by patterning the wiring linesfor the active shield at the time of patterning the wiring lines 5A and5B, there is no great increase in the time required for manufacturingthe semiconductor device. The wiring lines for the active shield aresupplied with the same voltage as that for the wiring lines 5A and 5Bshown in FIG. 19, for example. That is, the wiring lines for the activeshield are supplied with a low potential-side supply voltage (GND, forexample, 0V) and a high potential-side supply voltage (VCC, for example,1.8V, 3.0V, 5.0V), or a voltage other than those supply voltages.Alternatively, a portion of the wiring lines for the active shield maybe supplied with a low potential-side supply voltage and another portionthereof may be supplied with a high potential-side supply voltage.Further, a portion of the wiring lines for the active shield may besupplied with a potential other than the above-mentioned supplyvoltages. By thus disposing plural types of wiring lines for the activeshield, having different in supply potentials, within the same chip, itis possible to make decryption of the active shield system difficult;and, hence, it is possible to make efforts at cancellation or causingfailure of the active shield system to operate more difficult, so thatit is possible to make the analysis of information stored in the IC cardmore difficult.

[0123]FIG. 20 is an explanatory diagram showing an example of wiringlines 5C and 5D (the above-mentioned specific wiring lines, first wiringlines) for the active shield which constitute the active shield disposedin the area LA in FIG. 19. FIG. 21 is an enlarged plan view of aprincipal portion of FIG. 20.

[0124]FIGS. 20 and 21 show an example of an active shield having wiringlines 5C and 5D, which are comb teeth-like as seen in plan view. Thewiring lines 5C and 5D overlie signal lines such as bus lines 18 a, 18 band control signal lines 18 c to 18 e through an interlayer insulatingfilm. The wiring lines 5C and 5D are arranged so as to cover the signallines and so that the respective teeth are in engagement with eachother. Further, the spacing between both wiring lines 5C and 5D is setas narrow as possible so that the underlying signal lines, including buslines 18 a, 18 b and control signal lines 18 c to 18 e, cannot beobserved (see FIG. 21). That is, the wiring lines 5C and 5D are formedover the underlying signal lines, such as bus lines 18 a, 18 b andcontrol signal lines 18 c to 18 e, and are arranged in such a mannerthat the main extending direction of the wiring lines 5C and 5C isaligned with the main extending direction of the underlying signallines. Therefore, even if an attempt is made to apply a needle to asignal line which underlies the wiring lines 5C and 5D with theintention of analyzing information stored in the chip 3, it cannot bedone because these lines are obstructed by the wiring lines 5C and 5D.Accordingly, in such a structure as provided by this eighth embodiment,it is necessary to remove the wiring lines 5C and 5D to obtain access tothe underlying lines. However, if even a portion of the wiring lines 5Cand 5D is removed, the active shield system operates and the integratedcircuit fails to operate, thus making the analysis of informationimpossible. That is, it is possible to improve the security ofinformation stored in the IC card. In this eighth embodiment, moreover,the wiring lines 5C and 5D are arranged so that the underlying signallines are invisible. Further, the wiring width and spacing of the wiringlines 5C and 5D are set at values (minimum processing size) equal tothose of the underlying signal lines. By thus making the wiring lines5C, 5D for the active shield and the underlying signal lines similar insize and position to each other, it is possible to make it easier to seewhich lines are true signal lines. In other words, it is possible tomake the analysis of information stored in the IC card more difficult.For example, a supply voltage (GND, for example, 0V) on a low potentialside is applied to the wiring line 5C and a supply voltage (VCC, 1.8V,3.0V, 5.0V, for example) on a high potential side is applied to thewiring line 5D.

[0125] As shown in FIG. 20, plural processing detector circuits 20 maybe electrically connected to each of the wiring lines 5C and 5D for theactive shield. The processing detector circuits 20 may be connected toany positions (end part, middle position, position of the comb teeth) ofthe wiring lines 5C and 5D for the active shield. Further, oneprocessing detector circuits 20 may be electrically connected to both ofthe two wiring lines 5C and 5D. It is preferable that the position wherethe processing detector circuits 20 are located, the connecting positionwhere the wiring lines 5C and 5D for the active shield are connected tothe processing detector circuits 20, and the number of the processingdetector circuits 20 connected to each of the wiring lines 5C and 5D,will be irregular. Further, it is preferable that different distances bemixed between the processing detector circuits 20 and the wiring lines5C, 5D for the active shield. As a result, it is possible to makedecryption of the active shield system more difficult, and, hence, it ispossible to make efforts at cancellation or causing failure of theactive shield system to operate more difficult. Thus, the analysis ofinformation stored in the IC card can be made more difficult, and,hence, it becomes possible to further improve the security of the ICcard.

[0126] (Ninth Embodiment)

[0127] In connection with this ninth embodiment, a description will begiven of an example in which wiring lines for the supply voltage havinga shielding function and wiring lines for the active shield are arrangedat the same position planarly, but in different wiring layerssectionally.

[0128]FIG. 22 is a diagram of a layout of the layer structure of asemiconductor device according to the ninth embodiment of the presentinvention, FIG. 23 is a plan view of a principal portion of FIG. 22, andFIG. 24 is a plan view of FIG. 23 with the shield removed. As shown inFIG. 22, in a bottom layout layer L0, plural integrated circuit regionsare arranged, having desired elements which constitute, for example,cells, modules, as well as the foregoing memory circuit 3 a, logiccircuit group 3 b and processing detector circuits. In a wiring layer L1which overlies the layout layer L0 there are arranged signal lines 18,such as the foregoing bus lines 18 a, 18 b and control signal lines 18 cto 18 e. In a wiring layer L2 which overlies the wiring layer L1, thereis disposed a wiring line (specific wiring line, first wiring line) 5Efor an active shield, which has been described in conjunction with thesixth to eighth embodiments. In the illustrated example, there is showna single meandering wiring line (one-stroke wiring line) serving as thewiring line 5E for the active shield. For example, a supply voltage(GND, for example, 0V) on the low potential side and a supply voltage(VCC, 1.8V, 3.0V, 5.0V, for example) on the high potential side, or avoltage other than those supply voltages, is applied to the wiring line5E for the active shield. Plural processing detector circuits 20 areelectrically connected to the wiring line 5E (see FIG. 23). Theprocessing detector circuits 20 connected to the wiring line 5E are thesame as those described in connection with the sixth to eighthembodiments, and, therefore, an explanation thereof will be omitted.Further, in a top wiring layer L3, which overlies the wiring layer L2,there are wiring lines 5A and 5B for the supply voltage having ashielding function, which have been described in conjunction with thefirst to fifth embodiments. Thus, in this ninth embodiment, the supplyvoltage wiring lines 5A, 5B having a shielding function and the wiringline 5E for the active shield are at the same planar position and indifferent wiring layers. By adopting such a multi-layer structure,wherein wiring lines having a shielding function are stacked in multiplelayers at the same planar position and in different wiring layersthrough interlayer insulating films, or by arranging wiring lines havingthe same shielding function, but are different in technique, it ispossible to make decryption of the shield system more difficult, and itis possible to make efforts at cancellation or causing failure of theshield system to operate more difficult, so that the analysis ofinformation stored in the IC card can be made more difficult.Consequently, it becomes possible to further improve the security of theIC card. The relation in the vertical direction between the wiring layer5A, 5B for the supply voltage and that of the wiring layer 5E for theactive shield may be reversed. Between the wiring layer L3 with thesupply voltage wiring lines 5A, 5B formed therein and the wiring layerL2 with the wiring line 5E for active shield formed therein, there maybe interposed another wiring layer having a layout of supply voltagewiring lines possessing a shielding function and a wiring line forproviding an active shield. Between the layout layer L0 and the wiringlayer L1, between the wiring layers L1 and L2, and between the wiringlayers L2 and L3, there is provided an interlayer insulating film, e.g.,a silicon oxide film. That is, the wiring lines formed in each of thewiring layers L0, L1, L2, and L3 and the wiring lines formed in theadjacent upper and lower wiring layers are electrically isolated fromeach other by an interlayer insulating film, and those wiring lines areelectrically interconnected through connecting holes formed in eachinterlayer insulating film.

[0129] In this ninth embodiment, as shown in FIG. 23, the wiring lines5A, 5B for the supply voltage, which have a shielding function, and thewiring line 5E for the active shield are arranged at the same position(in the same wiring layer) as seen in plan view. Between adjacent wiringlines 5A and 5B for the supply voltage having a shielding function,there is disposed the underlying wiring line 5E for the active shield.Thus, by filling up the gap between adjacent supply voltage wiring lines5A and 5B having a shielding function with the underlying wiring line 5Efor the active shield, as shown in FIGS. 23 and 24, signal wiring lines18, such as bus lines and control signal lines which underlie the wiringline 5E for the active shield, can be made more difficult to see,thereby making the application of a needle to the wiring lines 18 andthe analysis of information with a FIB or the like more difficult.Consequently, it becomes possible to further improve the security of theIC card. As in the eighth embodiment, the wiring width and spacing ofthe wiring lines 5A, 5B, and 5E are set at the same values (minimumprocessing size) as those of the signal wiring lines 18, whereby theanalysis of information stored in the IC card can be made moredifficult, similar to the eighth embodiment.

[0130] (Tenth Embodiment)

[0131] In this tenth embodiment, a description will be given of the casewhere a shield area is subdivided into plural areas and shieldsdifferent in shape or technique are arranged respectively in thesubdivided areas.

[0132]FIG. 25 shows a shield area SA for the arrangement of shieldstherein, and FIGS. 26 to 29 show plan views of examples of wiring linesfor the active shield that are different in shape.

[0133] In this tenth embodiment, as shown in FIG. 25, the shield area(first area) SA is divided into nine sub-shield areas (second areas)SSA1 to SSA9, for example. In the illustrated example, the sub-shieldareas LA1 to LA9 are the same in both shape and area. The shield area SAmay be the whole of the main surface of the chip 3, or it may be onlythe wiring area (corresponding to the area LA) or circuit area on themain surface of the chip 3.

[0134]FIG. 26 illustrates wiring lines 5C and 5D for the active shield,which are arranged in the sub-shield area SSA1. The wiring lines 5C and5D for the active shield, as shown in FIG. 26, are comb teeth-shapedlike that described previously in connection with FIG. 20.

[0135]FIG. 27 illustrates a wiring line 5E for the active shield, whichis disposed in the sub-shield area SSA2. The wiring line 5E for theactive shield, as shown in FIG. 27, has a meandering shape like thatdescribed previously in connection with FIGS. 22 and 23.

[0136]FIG. 28 illustrates a wiring line (specific wiring line, firstwiring line) 5F for the active shield, which is disposed in thesub-shield area SSA3 shown in FIG. 25. The wiring line 5F, as shown inFIG. 28, has a complex intricate shape so that the meandering wiringline covers and hides the underlying signal lines and elements. Forexample, a supply voltage (GND, for example 0V) on the low potentialside or a supply voltage (VCC, 1.8V, 3.0V, 5.0V) on the high potentialside is applied to the wiring line 5F. FIG. 29 illustrates wiring lines5C and 5E for the active shield, which are arranged in the sub-shieldarea SSA4 shown in FIG. 25. The wiring line 5C for the active shield, asshown in FIG. 29, has the same comb teeth-shape as that describedearlier in connection with FIG. 20, while the wiring line 5E for theactive shield, as shown in FIG. 29, has the same meandering shape asthat described earlier in connection with FIGS. 22, 23 and 27. Thewiring lines 5C and 5E are arranged in such a manner that the teeth ofthe wiring line 5C project into concave gaps of the wiring line 5E so asto cover and hide the underlying signal lines and elements. By thusarranging active shield wiring lines 5C, 5D, 5E, and 5F of various shapein the shield area SA, it is possible to make the decryption of theshield system difficult and to make efforts at cancellation and causingfailure of the same system to operate also difficult, so that theanalysis of information stored in the IC card can be made moredifficult, and it becomes possible to further improve the security ofthe IC card. It is optional whether the wiring lines 5C, 5D, 5E, and 5Ffor the active shield are to be arranged in the same wiring layer or indifferent wiring layers. As in the eighth and ninth embodiments, thewiring width and spacing of the wiring lines 5C to 5F are set at values(minimum processing size) equal to those of the signal lines 18, wherebyit is possible to make the analysis of information stored in the IC carddifficult, as in the eighth and ninth embodiments. As to theconstruction of each processing detector circuit 20 and in what statethe processing detector circuits 20 are arranged with respect to thewirings 5C to 5F, they are the same as in the sixth to ninthembodiments, and, therefore, an explanation thereof will be omitted.

[0137] The shape of the wirings for the active shield is not limited tothe above-mentioned shape, but various changes may be made so long asthe shape that is adopted can cover and hide the underlying signal linesand elements. It is not necessary that the wiring lines for the activeshield arranged in the sub-shield areas SSA1 to SSA9 must all be madedifferent in shape, but wiring lines for the active shield having thesame shape also may be arranged in different sub-shield areas SSA1 toSSA9. Although reference has been made to only the active shield, thewiring lines 5A and 5B for the supply voltage and having a shieldingfunction, as described in connection with the first to fifthembodiments, may be arranged in different shapes for each of thesub-shield areas SSA1 to SSA9. An arrangement also may be adoptedwherein the wiring lines 5A and 5B for the supply voltage and having ashielding function are arranged in any of the sub-shield areas SSA1 toSSA9 and the wiring lines for the active shield are arranged in theother sub-shield areas. In this way, it is possible to make decryptionof the shield system more difficult, and it is also possible to makeefforts at cancellation and causing failure of the shield system tooperate difficult, so that the analysis of information stored in the ICcard can be made more difficult, and it becomes possible to furtherimprove the security of the IC card.

[0138]FIGS. 30 and 31 show examples of the layout of wiring lines forthe active shield arranged in the sub-shield areas SSA1 to SSA9, ofwhich FIG. 30 shows a case where one pair of wiring lines 5C and 5D forthe active shield are arranged in the sub-shield area SSA1, and FIG. 31shows a case where plural pairs of wiring lines 5C and 5D for the activeshield are arranged in the sub-shield area SSA1. In FIG. 1, verticallyasymmetrically arranged pairs and vertically symmetrically arrangedpairs are mixed together. According to this arrangement, it is possibleto make decryption of the shield system difficult, and it is alsopossible to make efforts at cancellation and causing failure of theshield system to operate difficult, so that the analysis of informationstored in the IC card can be made more difficult, and, hence, it ispossible to further improve the security of the IC card.

[0139] In each of the first to ninth embodiments, by arranging a shieldof a different shape or technique for each of such subdivided areas, asprovided in this embodiment, it is possible to make the analysis ofinformation in the IC card more difficult, and, therefore, the securityof the IC card can be further improved.

[0140] (Eleventh Embodiment)

[0141] In connection with this eleventh embodiment, a description willbe given of a case where the planar positional relation between wiringlines for the active shield and the detector circuits connectedelectrically thereto is irregular.

[0142] It does not matter where the processing detector circuits whichconstitute the active shield system are to be connected to the wiringlines for the active shield. However, if the relation of the connectionbetween the processing detector circuits and the wiring lines for theactive shield is decrypted and the position of the processing detectorcircuits becomes clear, there is a fear that the processing detectorcircuits may be destroyed to prevent them from carrying out theshielding function. In this eleventh embodiment, in view of such aninconvenience, the wiring lines for the active shield and the processingdetector circuits connected electrically thereto are arranged so as tobe irregular in planar positional relation. FIG. 32 shows an example ofsuch a layout. In this figure, three sub-shield areas SSA1, SSA3, SSAn,are shown, and three processing detector circuits 20 a 1, 20 a 3, 20 an(20) corresponding thereto, respectively, are provided. Correspondingsub-shield areas and processing detector circuits are hatched so as toclarify the relation of the correspondence therebetween. The processingdetector circuit 20 a 1, which is connected to a predetermined activeshield wiring line, that is disposed in the sub-shield area SSA1 in atop wiring layer L3, is disposed in a layout layer L0 at a position thatis not just under the sub-shield area SSA1, but is at a differentirregular planar position. Also, as to the other sub-shield areas SSA3and SSAn in the wiring layer L3, the processing detector circuits 20 a 3and 20 an, which are connected to the active shield wiring lines inthose sub-shield areas, are arranged in the layout layer L0 withoutregularity relative to the arranged positions of the sub-shield areasSSA3 and SSAn. Consequently, it is possible to make decryption difficultwith respect to the positional and connectional relations between thewiring lines for the active shield in the sub-shield areas SSA1, SSA3,SSAn and the processing detector circuits 20 (20 a 1, 20 a 3, 20 an),and it is also possible to make attempts at cancellation and causingfailure of the shield system to operate more difficult, so that theanalysis of information stored in the IC card can be made moredifficult, and it is possible to further improve the security of the ICcard.

[0143] By applying to each of the sixth to tenth embodiments a layout inwhich the planar positional relation between the wiring lines for theactive shield and the detector circuits connected electrically thereto,as provided in this embodiment, it is possible to make the analysis ofinformation stored in the IC card more difficult, and the security ofthe IC card can be further improved.

[0144] (Twelfth Embodiment)

[0145] In this twelfth embodiment reference will be made to an examplein which plural processing detector circuits are electrically connectedto a predetermined active shield wiring line. FIG. 33 shows an exampleof an active shield system according to this embodiment, in which pluralsub-shield areas SSA are arranged. The sub-shield areas SSA correspondto the foregoing sub-shield areas SSA1 to SSA9. In each sub-shieldactive area SSA there is disposed a wiring line for the active shield.The active shield wiring lines in the sub-shield areas SSA may be thesame or different. Plural processing detector circuits 20 are connectedelectrically to the active shield wiring line in each sub-shield areaSSA. The active shield wiring lines and the processing detector circuits20 are connected together randomly in a wiring layer disposedintermediate between a wiring layer including a layout layer L0 and theforegoing principal signal lines and a wiring layer wherein the wiringlines for the active shield are arranged. The connectional relationbetween the wiring lines for the active shield and the processingdetector circuits 20 is made so complicated as to make the decryptionthereof difficult. The area of each sub-shield area SSA is kept to aminimum, and each active shield wiring line is monitored by pluralprocessing detector circuits 20. In this way, even if one processingdetector circuit 20 is destroyed and invalidated, the information storedin the IC can be protected, because another processing detector circuit20 will operate. By subdividing the shield area SA into sub-shield areasSSA of a small area, an entire shield wiring layout in the shield areaSA and the connectional relation thereof to the processing detectorcircuits 20 can be made more complicated, so that it is possible to makedecryption of the shield system difficult, and it is possible to improvethe IC card security.

[0146] By applying to each of the sixth to eleventh embodiments a layoutsuch as provided in this embodiment, wherein plural processing detectorcircuits are connected electrically to a predetermined wiring line forthe active shield, the analysis of information stored in the IC card canbe made more difficult, and it is possible to further improve thesecurity of the IC card.

[0147] (Thirteenth Embodiment)

[0148] In connection with this thirteenth embodiment, reference will bemade to a case where the potential of a wiring line for the activeshield is not made constant, but is varied with the lapse of time.

[0149]FIG. 34 is a diagram showing an example of an active shield systemaccording to the thirteenth embodiment of the present invention. In thissystem, a predetermined potential is supplied from a potential supplycircuit 25 formed in the chip 3 to a wiring line (5E in FIG. 34) for theactive shield. The potential supply circuit 25 changes the potentialthat is fed to the wiring line 5E in synchronism with a synchronizingsignal provided from an independent oscillator 26 formed within the chip3. The synchronizing signal from the oscillator 26 is also applied to aprocessing detector circuit 20 through a synchronizing signal line 27 sothat, also on the processing detector circuit 20 side, a proper-or-notreference potential is changed to match the synchronizing signal fedfrom the oscillator 26. The proper-or-not reference potential is areference potential serving as a reference of comparison when judgingwhether the potential of the active shield wiring line 5E, which isdetected by the processing detector circuit 20, is proper or not. If theproper-or-not reference potential is equal to the detected potential,(including an allowable error), the detected potential is judged to beproper. More specifically, in the processing detector circuit 20, thepotential of the active shield wiring line 5E, which is detected at apredetermined time, is compared with the proper-or-not referencepotential detected at the predetermined time, and upon detection of adifference between both potentials, the processing detector circuit 20resets the integrated circuit in the chip 3 so as to make the integratedcircuit unable to operate, thereby preventing the analysis ofinformation stored in the IC card. Thus, since efforts at cancellationand causing failure of the active shield system to operate can be madedifficult by changing the potential of the active shield wiring line 5E,it is possible to make the analysis of information stored in the IC cardmore difficult, and the security of the IC card can be further improved.The oscillator 26 is adapted to operate upon turning ON of the powersupply.

[0150] By applying to each of the sixth to twelfth embodiments, theconstruction of this embodiment, wherein the potential of the activeshield wiring line is not made constant, it is possible to make theanalysis of information stored in the IC card more difficult, and thesecurity of the IC card can be further improved.

[0151] (Fourteenth Embodiment)

[0152] In connection with this fourteenth embodiment, reference will bemade to another example in which the potential of a wiring line for theactive shield is not constant, but is varied with the lapse of time.

[0153] In connection with this fourteenth embodiment, the potentialswitching time for an active shield wiring line is irregular. FIG. 35 isa diagram showing an example of an active shield system according tothis fourteenth embodiment. In this system, a frequency divider circuit29 is turned ON or OFF in response to a signal provided from a randomnumber generator circuit 28, thereby changing the frequency of asynchronizing signal that is outputted from the oscillator 26. In thisfourteenth embodiment, the frequency of the synchronizing signaloutputted from the oscillator 26 is changed irregularly through thefrequency divider circuit 26. In synchronism with the synchronizingsignal provided from the frequency divider circuit 29, a potentialsupply circuit 25 changes the potential fed to a wiring line (5E in FIG.35) for the active shield. Therefore, in this fourteenth embodiment, thepotential of the active shield wiring line 5E does not changeperiodically, but changes at irregular times. Further, the synchronizingsignal provided from the frequency divider circuit 29 is applied also tothe processing detector circuit 20 through a synchronizing signal line27. In accordance with the synchronizing signal provided from thefrequency divider circuit 29, the processing detector circuit 20 changesthe proper-or-not reference signal described in the previous thirteenthembodiment. Thus, in this fourteenth embodiment, even if the potentialof the active shield wiring line 5E varies irregularly, it is possibleto change the proper-or-not reference potential of the processingdetector circuit 20 accordingly. The processing detector circuit 20compares the potential of the active shield wiring line 5E that isdetected at a predetermined time with the proper-or-not referencepotential to be detected at the predetermined time; and, upon detectionof a difference between both potentials, the processing detector circuit20 resets the integrated circuit in the chip 3 so as to render theintegrated circuit unable to operate, as in the thirteenth embodiment,thereby preventing the analysis of information stored in the IC card. Bythus making the timing of the potential change of the wiring line 5E foractive shield irregular, the timing can be made difficult to read.Further, it is possible to make any effort to effect cancellation and tocause failure of the active shield system to operate more difficult, andthe analysis of information stored in the IC card can be made moredifficult, so that it becomes possible to further improve the securityof the IC card. The active shield system in this fourteenth embodimentand that in the previous thirteenth embodiment may be mixed together inthe same chip 3, whereby it becomes more difficult to decrypt the activeshield systems in the chip 3, and, therefore, it becomes possible tofurther improve the security of the IC card.

[0154] By applying to each of the sixth to thirteenth embodiments theconstruction of this embodiment, wherein the potential of the activeshield wiring line is not kept constant, but is varied with the lapse oftime, it is possible to make the analysis of information stored in theIC card more difficult, and the security of the IC card can be furtherimproved.

[0155] (Fifteenth Embodiment)

[0156] In connection with this fifteenth embodiment, reference will bemade to another example in which the potential of a wiring line foractive shield is not made constant, but is varied with the lapse oftime.

[0157] In this fifteenth embodiment, a signal having a predeterminedfrequency is allowed to flow in a wiring line of the active shield, andwhen the signal of that frequency can not be detected, control iseffected to make the integrated circuit in the chip 3 unable to operate.FIG. 36 shows an example of an active shield system for a semiconductordevice according to the fifteenth embodiment of the present invention.

[0158] A signal of a predetermined frequency generated by an oscillator26 is transmitted to a wiring line (5E in FIG. 36) for the activeshield. While the signal of the predetermined frequency is flowing inthe wiring line 5E for the active shield, the processing detectorcircuit 20 does not operate at all, but when the potential of the activeshield wiring line 5E is fixed to high or low levels direct-currentwise,the processing detector circuit 20 detects it and resets the integratedcircuit in the chip 3, thereby disabling the integrated circuit so as toprevent the analysis of information stored in the IC card.

[0159] According to this fifteenth embodiment, the following effects canbe obtained in addition to the effects obtained in the thirteenth andfourteenth embodiments. Since the construction of the shield system issimple and it is difficult to destroy, it is possible to make an effortto effect cancellation and to cause failure of the active shield systemto operate more difficult, and, hence, it is possible to make theanalysis of information stored in the IC card more difficult, whereby itbecomes possible to further improve the security of the IC card.Besides, since the construction of the shield system is simple, thesemiconductor device manufacturing process does not become complicated.Moreover, it is possible to decrease the layout area of elements andwiring lines for the active shield system in comparison with thethirteenth and fourteenth embodiments. Further, the active shield systemin this fifteenth embodiment and the active shield system in thethirteenth and fourteenth embodiments may be mixed together in the samechip 3, whereby the decryption of the shield system in the chip 3becomes more difficult, and, thereby, it is possible to further improvethe security of the IC card.

[0160] By applying to each of the sixth to fourteenth embodiments theconstruction of this embodiment, wherein the potential of the wiringline for the active shield is not made constant, but is varied with thelapse of time, whereby the analysis of information in the IC card can bemade more difficult, and it is possible to further improve the securityof the IC card.

[0161] (Sixteenth Embodiment)

[0162] In connection with this sixteenth embodiment, reference will bemade to an example in which different active shield wiring lines arearranged in the same wiring layer. FIG. 37 shows an example of thelayout of wiring lines 5C, 5D, and 5E for the active shield according tothis sixteenth embodiment. In this sixteenth embodiment, active shieldwiring lines 5C, 5D, and 5E having different shapes are arranged in thesame wiring layer in the chip 3. The shapes of the wiring lines 5C, 5D,and 5E are the same as in the eighth to tenth embodiments. The layout ofthe wiring lines 5C and 5D is the same as in the eighth and tenthembodiments. The wiring line 5E is disposed in a gap between adjacentwiring lines 5C and 5D so as to cover and hide underlying signal lines18 and other elements. As in the eighth to tenth embodiments, pluralprocessing detector circuits 20 are electrically connected to each ofthe wiring lines 5C, 5D, and 5E. Also, in this sixteenth embodiment, itis possible to improve the security of the IC card.

[0163] By applying to each of the sixth to fifteenth embodiments theconstruction of this sixteenth embodiment, wherein different activeshield wiring lines are arranged in the same wiring layer, it ispossible to make the analysis of information stored in the IC card moredifficult, and, therefore, the security of the IC card can be furtherimproved.

[0164] (Seventeenth Embodiment)

[0165] In connection with this seventeenth embodiment, reference will bemade to another example in which a shield area is subdivided into pluralsub-shield areas. FIG. 38 is a plan view showing an example of a shieldarea SA, in which Xa1, Xa2, . . . Xa6 represent X coordinates and Ya1,Ya2, . . . Ya6 represent Y coordinates.

[0166] Also, in this seventeenth embodiment, the shield area SA issubdivided into plural sub-shield areas SSA, provided the sub-shieldareas SSA are mutually different in area and the various shapes thereofare arranged irregularly. Thus, the layout of the sub-shield areas SSAin the shield area SA are asymmetric vertically and transversely. As inthe tenth embodiment, wiring lines for the active shield that aredifferent in shape are arranged in each sub-shield area SSA, whereby itis possible to make decryption of the active shield system difficult,and, hence, it is possible to improve the security of the IC card.

[0167] By applying to each of the sixth to sixteenth embodiments theconstruction of this embodiment, wherein the shield area is subdividedinto plural sub-shield areas, it is possible to make decryption ofinformation stored in the IC card more difficult, and the security ofthe IC card can be further improved.

[0168] (Eighteenth Embodiment)

[0169] In connection with this eighteenth embodiment, reference will bemade to a further example in which a shield area is subdivided intoplural sub-shield areas.

[0170] In this eighteenth embodiment, the subdividing of the shield areais changed for each chip which constitutes an IC card or for eachproduction of a semiconductor device. FIG. 39 is a plan view showing anexample of a shield area SA. In FIG. 39, like FIG. 38, the shield areaSA is subdivided into plural sub-shield areas SSA, which sub-shieldareas, however, are different in shape and layout from those shown inFIG. 38. In this eighteen embodiment, even in the same wafer, the shieldarea SA shown in FIG. 38 is used for certain chips and the shield areaSA shown in FIG. 39 is used for other chips. Alternatively, the shieldarea SA shown in FIG. 38 is used for all of the chips in a certainwafer, and the shield area SA shown in FIG. 39 is used for all of thechips in another wafer. In this way, even if the shield system in onechip is decrypted, this does not directly lead to the possibility ofdecrypting the shield system in another chip. Consequently, it ispossible to make decryption of an active shield system difficult, and,hence, it is possible to improve the security of the IC card.

[0171] By applying to each of the sixth to seventeenth embodiments theconstruction of this embodiment, wherein the shield area is subdividedinto plural sub-shield areas, it is possible to make the analysis ofinformation stored in the IC card more difficult, and, further, toimprove the security of the IC card.

[0172] (Nineteenth Embodiment)

[0173] In connection with this nineteenth embodiment, reference will bemade to an example in which different shield areas are stacked inmultiple layers. More specifically, the active shield wiring lines inthe shield areas shown in FIGS. 38 and 39 are arranged at the sameplanar position on the chip 3 and in different wiring layers, whereby,when seen in plan view, the superposition of the active shield wiringlines can be made more complicated, and, therefore, it is possible tomake decryption of the active shield system difficult. Consequently, itbecomes possible to improve the security of the IC card.

[0174] The active shield wiring lines in different wiring layers may beconnected together electrically via through holes or the like. Thethrough holes are fine holes formed through an interlayer insulatingfilm which is interposed between different wiring layers, and aconnecting conductor is embedded in the interior of each through hole.In this case, by changing the layout position of the through holes foreach chip, the wiring route of the active shield system can be changedby a relatively simple method in both design and process. Moreparticularly, even when the active shield wiring lines in differentchips may appear equal in planar layout at first glance, there is anentirely different wiring route of the active shield system in differentchips due to a difference in the layout of the through holes. Besides,the through holes are so fine that, by a mere glance at the throughholes as seen in plan view, it is difficult to search for the wiringroute, and, therefore, it is possible to make decryption of the activeshield system difficult, thus permitting improvement in the security ofthe IC card.

[0175] By applying to each of the sixth to eighteenth embodiments theconstruction of this embodiment, wherein different shield areas arestacked in multiple layers, it is possible to make the analysis ofinformation stored in the IC card more difficult, and the security ofthe IC card can be further improved.

[0176] Although the present invention has been described abovespecifically on the basis of various embodiments thereof, it goeswithout saying that the present invention is not limited to thoseembodiments, but that various changes may be made within a scope notdeparting from the gist of the invention.

[0177] For example, although the sixth and seventh embodiments have beendescribed with reference to a case where, if a wiring line for detectinga processing using a processing detector circuit is cut off, the cuttingis detected, the invention is not limited thereto. There may be adopted,for example, a construction wherein, even when the wiring line fordetecting a processing is not cut off completely, but is cut partiallyand is connected partially, a change in potential is detected byutilizing the phenomenon that the potential of the processing detectingwiring line is varied by the processing, thereby resetting theintegrated circuit.

[0178] Although the first to seventh embodiments have been describedwith reference to a case where the present invention is applied to aso-called contact type IC card, wherein the reading and writing ofinformation for the chip are carried out through electrodes formed onthe back side of the package substrate, the invention is not limitedthereto, but is applicable to various other types of IC cards. Forexample, the present invention is also applicable to a so-callednon-contact type IC card, wherein a coil (antenna) is provided within acard body and the reading and writing of data are carried out byutilizing radio waves in a non-contact manner using a reader/writer.

[0179] Moreover, by combining each of the first to nineteenthembodiments with one or more of the other embodiments included in thefirst to nineteenth embodiments, it is possible to make the decryptionof information stored in the IC card more difficult, and the security ofthe IC card can be further improved.

[0180] It goes without saying that the wiring structures of the first tonineteenth embodiments are not limited to the illustrated ones, butthere may be a metallic multi-layer wiring structure comprising five toten layers.

[0181] Although the present invention has been described above mainlywith reference to its application to an IC card as a backgroundapplication field of the invention, the invention is not limitedthereto, but is applicable, for example, to all products having asemiconductor device which stores information.

[0182] In short, according to the constructions of the aboveembodiments, wiring lines 5A and 5B for the supply of a voltage to feeda drive voltage to the integrated circuit in the semiconductor chip 3are arranged so as to cover the main surface of the semiconductor chip3, and if the wiring lines 5A and 5B are removed for the purpose ofanalyzing information stored in the semiconductor chip 3, the integratedcircuit fails to operate, making it impossible to analyze theinformation. Thus, if predetermined wiring lines arranged in an upperlayer of the semiconductor chip are removed or cut off, it becomesimpossible to analyze information stored in the chip, whereby it ispossible to improve the security of information stored in thesemiconductor chip.

[0183] Further, processing detector circuits 20 for detecting aprocessing of the wiring lines 5A and 5B are provided, which, upondetection of a processing of the wiring lines 5A and 5B, operate toreset the integrated circuit. With such processing detector circuits, itis impossible to analyze information stored in the semiconductor chip,and, therefore, the security of information stored in the semiconductordevice can be improved.

[0184] The present invention is useful as a semiconductor device for useas a medium for the storage of various items of information in variousfields, including electronic money, credit card, portable telephone,chargeable satellite broadcast receiver, identification card, license,insurance policy, electronic medical sheet, electronic railway ticket,finance, distribution, medical care, traffic, transportation, andeducation, and it is particularly suitable in its application to an ICcard.

1. A semiconductor device comprising: (a) a first element formed over amain surface of a semiconductor chip and contributing to the storage ofinformation; (b) a second element formed over the main surface of thesemiconductor chip; (c) a first area formed over the main surface of thesemiconductor chip and divided into a plurality of second areas; (d) adesired signal line formed in the first area; and (e) wiring lines forsupply voltage contributing to the actuation of the first and secondelements, the wiring lines for supply voltage being disposedrespectively in the plural second areas in a layer which overlies thedesired signal line so as not to permit the analysis of informationunless they are cut off or removed, and being formed so as to bedifferent in shape.
 2. A semiconductor device comprising: (a) a firstelement formed over a main surface of a semiconductor chip andcontributing to the storage of information; (b) a second element formedover the main surface of the semiconductor chip; (c) a first areadisposed over the main surface of the semiconductor chip and dividedinto a plurality of second areas so as to cover the main surface of thesemiconductor chip; (d) a desired signal line formed in at least one ofthe plural second areas; and (e) a wiring line for supply voltagecontributing to the actuation of the first and second elements anddisposed respectively in the plural second areas in a layer whichoverlies the desired signal line, the wiring lines for supply voltagebeing formed so as to be different in shape.
 3. A semiconductor devicecomprising: (a) a first element formed over a main surface of asemiconductor chip and contributing to the storage of information; (b) asecond element formed over the main surface of the semiconductor chip;(c) a first area disposed over the main surface of the semiconductorchip and divided into a plurality of second areas; (d) desired signalline formed in the first area; and (e) wiring lines for supply voltagecontributing to the actuation of the first and second elements andpartially respectively in the plural second areas so as to cover thedesired signal line in a layer which overlies the desired signal line,and being formed so as to be different in shape.
 4. A semiconductordevice according to any of claims 1 to 3, wherein, when the wiring linefor supply voltage is cut off or removed, a supply voltage is not fed tothe first or the second element and a circuit does not operate.
 5. Asemiconductor device according to any of claims 1 to 3, wherein thewiring line for supply voltage comprises a wiring line for supplyvoltage on a high potential side which supplies a relatively high supplyvoltage and a wiring line for supply voltage on a low potential sidewhich supplies a relatively low supply voltage, and wherein the wiringline for supply voltage on a high potential side and the wiring line forsupply voltage on a low potential side are planarly deviated from eachother in such a manner that one is interposed in gaps formed in theother and the other is interposed in gaps formed in the one.
 6. Asemiconductor device according to any of claims 1 to 3, wherein thewiring line for supply voltage comprises a wiring line for supplyvoltage on a high potential side which supplies a relatively high supplyvoltage and a wiring line for supply voltage on a low potential sidewhich supplies a relatively low supply voltage, and wherein the wiringline for supply voltage on a high potential side and the wiring line forsupply voltage on a low potential side are formed in the shape of combteeth and arranged planarly so that the respective teeth are in meshwith each other.
 7. A semiconductor device according to any of claims 1to 3, wherein the wiring line for supply voltage comprises a wiring linefor supply voltage on a high potential side which supplies a relativelyhigh supply voltage and a wiring line on a low potential side whichsupplies a relatively low supply voltage, and wherein the wiring linefor supply voltage on a high potential side and the wiring line forsupply voltage on a low potential side are formed in a lattice shape andarranged planarly so that one is interposed in gaps formed in the otherand the other is interposed in gaps formed in the one.
 8. Asemiconductor device according to any of claims 1 to 3, wherein thewiring line for supply voltage comprises a wiring line for supplyvoltage on a high potential side which supplies a relatively high supplyvoltage and a wiring line for supply voltage on a low potential sidewhich supplies a relatively low supply voltage, and wherein the wiringline for supply voltage on the high potential side and the wiring linefor supply voltage on the low potential side are solid wiring lines. 9.A semiconductor device comprising: (a) a first element formed over amain surface of a semiconductor chip and contributing to the storage ofinformation; (b) a first area disposed over the main surface of thesemiconductor chip and divided into a plurality of second areas; (c) adesired signal line formed in the first area; and (d) a detectorcircuits disposed respective in the plural second areas in a layer whichoverlies the desired signal line, the detector circuits, when firstwiring lines formed so as to be different in shape are cut off,detecting it and make it impossible to analyze information stored in thefirst element.
 10. (canceled)
 11. A semiconductor device according toclaim 9, wherein the first wiring line is a wiring line for supplyvoltage.
 12. A semiconductor device according to claim 11, wherein thewiring line for supply voltage comprises a wiring line for supplyvoltage on a high potential side which supplies a relatively high supplyvoltage and a wiring line for supply voltage on a low potential sidewhich supplies a relatively low supply voltage.
 13. A semiconductordevice according to claim 11, wherein the wiring line for supply voltageis constituted by a single wiring line which is disposed in apredetermined shape so as to cover the desired signal line.
 14. Asemiconductor device according to claim 11, wherein the wiring line forsupply voltage is constituted by a single wiring line in such a mannerthat, when the single wiring line is cut off, the cut-off wiringportions are completely isolated from each other.
 15. A semiconductordevice according to claim 9, wherein the detector circuit is dispersedplurally within the main surface of the semiconductor chip.
 16. Asemiconductor device according to claim 15, wherein the detector circuitis disposed in a circuit block area of the main surface of thesemiconductor chip.
 17. A semiconductor device according to claim 15 orclaim 16, wherein the detector circuit is disposed in a wiring area ofthe main surface of the semiconductor chip.
 18. A semiconductor deviceaccording to any of claims 12 to 14, wherein the wiring line for supplyvoltage is different from a wiring line for supply voltage whichsupplies a supply voltage for actuating the detector circuits.
 19. Asemiconductor device according to claim 9, wherein an input wiring lineof a predetermined one of said plural detector circuits is used as awiring line for supply voltage in the other detector circuit.
 20. Asemiconductor device comprising: (a) a first element formed over a mainsurface of a semiconductor chip and contributing to the storage ofinformation; (b) a second element formed over the main surface of thesemiconductor chip; (c) a first area disposed over the main surface ofthe semiconductor chip and divided into a plurality of second areas soas to cover the main surface of the semiconductor chip; and (d) adesired signal line formed in at least one of the plural second areas;and (e) wiring lines for supply voltage which contribute to actuatingthe first and second elements, the wiring lines for supply voltage beingeach constituted by a single wiring line in such a manner that, when thesingle wiring line is cut off, the cut-off wiring portions arecompletely isolated from each other so as not to actuate the first andsecond elements, the wiring line for supply voltage being disposedrespectively in the plural second areas in a layer which overlies thedesired signal line, and being formed so as to be different in shape.21. An IC card comprising: (a) a first element formed over a mainsurface of a semiconductor chip and contributing to the storage ofinformation; (b) a second element formed over the main surface of thesemiconductor chip; (c) a first area disposed over the main surface ofthe semiconductor chip and divided into a Plurality of second areas; (d)a desired signal line formed in the first area; (e) wiring lines forsupply voltage which contributes to actuating the first and secondelements, the wiring lines for supply voltage being disposedrespectively in the plural second areas in a layer which overlies thedesired signal line so as not to permit the analysis of informationunless it is cut off or removed, and being formed so as to be differentin shape; (f) a package for sealing the semiconductor chip; and (g)plate-like card body which receives the package within a groove.
 22. AnIC card comprising: (a) a first element formed over a main surface of asemiconductor chip and contributing to the storage of information; (b) asecond element formed over the main surface of the semiconductor chip;(c) a first area disposed over the main surface of the semiconductorchip and divided into a plurality of second areas so as to cover themain surface of the semiconductor chip; (d) a desired signal line formedin at least one of the plural second areas; (e) wiring lines for supplyvoltage which contributes to actuating the first and second elements,the wiring lines for supply voltage being disposed respectively in theplural second areas in a layer which overlies the desired signal line,and being formed so as to be different in shape; (f) a package forsealing the semiconductor chip; and (g) plate-like card body whichreceives the package within a groove.
 23. An IC card comprising: (a) afirst element formed over a main surface of a semiconductor chip andcontributing to the storage of information; (b) a second element formedover the main surface of the semiconductor chip; (c) a first areadisposed over the main surface of the semiconductor chip and dividedinto a Plurality of second areas; (d) a desired signal line formed inthe first area; (e) a wiring lines for supply voltage which contributesto actuating the first and second elements, the wiring line for supplyvoltage being partially disposed respectively in the plural second areasso as to cover the desired signal line in a layer which overlies thedesired signal line, and being formed so as to be different in shape;(f) a package for sealing the semiconductor chip; and (g) a plate-likecard body which receives the package within a groove.
 24. An IC cardcomprising: (a) a first element formed over a main surface of asemiconductor chip and contributing to the storage of information; (b) asecond element formed over the main surface of the semiconductor chip;(c) a first area disposed over the main surface of the semiconductorchip and divided into a plurality of second area; (d) a desired signalline formed in the first area (e) wiring lines for supply voltage whichcontributes to actuating the first and second elements, the wiring linesfor supply voltage being formed respectively in the plural second areasin a layer which overlies the designed signal line, the wiring lines forsupply voltage being formed so as to be different in shape, wherein whenthe wiring line for supply voltage is cut off or removed, a supplyvoltage is not fed to the first or the second element and a circuit doesnot operate.
 25. An IC card according to any of claims 21, 22, 23, and24, wherein the wiring line for supply voltage comprises a wiring linefor supply voltage on a high potential side which supplies a relativelyhigh supply voltage and a wiring line for supply voltage on a lowpotential side which supplies a relatively low supply voltage, and thewiring line for supply voltage on a high potential side and the wiringline for supply voltage on a low potential side are planarly deviatedfrom each other in such a manner that one is interposed in gaps formedin the other and the other is interposed in gaps formed in the one. 26.An IC card according to any of claims 21, 22, 23, and 24 wherein thewiring line for supply voltage comprises a wiring line for supplyvoltage on a high potential side which supplies a relatively high supplyvoltage and a wiring line for supply voltage on a low potential sidewhich supplies a relatively low supply voltage, and wherein the wiringline for supply voltage on a high potential side and the wiring line forsupply voltage on a low potential side are formed in the shape of combteeth and arranged planarly so that the respective teeth are in meshwith each other.
 27. An IC card according to any of claims 21, 22, 23,and 24 wherein the wiring line for supply voltage comprising a wiringline for supply voltage on a high potential side which supplies arelatively high supply voltage and a wiring line for supply voltage on arelatively low potential side which supplies a relatively low supplyvoltage, and wherein the wiring line for supply voltage on a highpotential side and the wiring line for supply voltage on a low potentialside are formed in a lattice shape and arranged planarly so that one isinterposed in gaps formed in the other and the other is interposed ingaps formed in the one.
 28. An IC card according to any of claims 21,22, and 23, wherein the wiring line for supply voltage comprises awiring line for supply voltage on a high potential side which supplies arelatively high voltage and a wiring line for supply voltage on a lowpotential side which supplies a relatively low supply voltage, andwherein the wiring line for supply voltage on a high potential side andthe wiring line for supply voltage on a low potential side are solidwiring lines.
 29. An IC card comprising: (a) a first element formed overa main surface of a semiconductor chip and contributing to the storageof information; (b) a second element formed over the main surface of thesemiconductor chip; (c) a first area disposed over the main surface ofthe semiconductor chip and divided into a plurality of second areas; (d)a desired signal line formed in the first area; (e) detector circuitsdisposed respectively in the plural second areas in a layer overlyingthe desired signal line and detecting, when first wiring lines formed soas to be different in shape are cut off, it and makes it impossible toanalyze information stored in the first element; (f) a package forsealing the semiconductor chip; and (g) a plate-like card body whichreceives the package within a groove.
 30. An IC card comprising: (a) afirst area disposed over a main surface of a semiconductor chip anddivided into a plurality of second areas; (b) first wiring lines formedin the first area; (c) a detector circuit for detecting a change inpotential of the first wiring line; (d) a package for sealing thesemiconductor chip; and (e) a plate-like card body which receives thepackage within a groove, wherein the first wiring lines are disposedrespectively in the plurally divided second areas and are formed so asto be different in shape.
 31. An IC card according to claim 29 or claim30, wherein the first wiring line is a wiring line for supply voltage.32. An IC card according to claim 31, wherein the wiring line for supplyvoltage comprises a wiring line for supply voltage on a high potentialside which supplies a relatively high supply voltage and a wiring linefor supply voltage on a low potential side which supplies a relativelylow voltage.
 33. An IC card according to claim 31, wherein the wiringline for supply voltage is constituted by a single wiring line which isdisposed in a predetermined shape so as to cover the desired signalline.
 34. An IC card according to claim 31, wherein the wiring line forsupply voltage is constituted by a single wiring line in such a mannerthat, when the single wiring line is cut off, the cut-off wiringportions are completely isolated from each other.
 35. An IC cardaccording to any of claims 29 and 30, wherein the detector circuit isdispersed plurally within the main surface of the semiconductor chip.36. An IC card according to claim 35, wherein the detector circuit isdisposed in a circuit block area of the main surface of thesemiconductor chip.
 37. An IC card according to claim 35, wherein thedetector circuit is disposed in a wiring area of the main surface of thesemiconductor chip.
 38. An IC card according to claim 31, wherein thewiring line for supply voltage is different from a wiring line forsupply voltage for actuating the detector circuits.
 39. An IC cardaccording to any of claims 29 and 30, wherein an input wiring line of apredetermined one of said plural detector circuits is used as a wiringline for supply voltage in the other detector circuit.
 40. An IC cardcomprising: (a) a first element formed over a main surface of asemiconductor chip and contributing to the storage of information; (b) asecond element formed over the main surface of the semiconductor chip;(c) a first area disposed over the main surface of the semiconductorchip and divided into a plurality of second areas so as to cover themain surface of the semiconductor chip; (d) a desired signal line formedin at least one of the plural second areas; (e) wiring lines for supplyvoltage which contributes to actuating the first and second elements,the wiring lines for supply voltage being each constituted by a singlewiring line in such a manner that, when the single wiring line is cutoff, the cut-off wiring portions are completely isolated from each otherso as not to actuate the first and second elements, the wiring lines forsupply voltage being disposed respectively in the plural second areas ina layer which overlies the desired signal line, and being formed so asto be different in shape; (f) a package for sealing the semiconductorchip; and (g) plate-like card body which receives the package within agroove.
 41. (canceled)
 42. (canceled)
 43. A semiconductor devicecomprising: (a) a first area disposed over a main surface of asemiconductor chip; (b) a plurality of second areas formed by dividingthe first area; (c) first wiring lines disposed respectively in thesecond area; and (d) a detector circuit for detecting a processing ofone of the first wiring lines which is disposed in a predetermined oneof the plural second areas.
 44. A semiconductor device according toclaim 43, wherein a wiring line for supply voltage which contributes toactuating an integrated circuit formed in the semiconductor chip isdisposed in a wiring layer different from a wiring layer in which thefirst wiring line is disposed, the wiring line for supply voltage beingdisposed in the first area so as to lie over the first wiring lineplanarly.
 45. A semiconductor device according to claim 44, wherein apattern of the first wiring line is disposed in a planar positioncorresponding to a gap between adjacent portions of a pattern of thewiring line for supply voltage.
 46. A semiconductor device according toany of claims 43, 44, and 45, wherein said plural first wiring linesdifferent in shape are disposed in the first area and in one and samewiring layer.
 47. A semiconductor device according to claim 46, whereinthe first wiring lines different in shape are disposed in such a mannerthat a pattern of one of said first wiring lines is interposed in a gapbetween adjacent portions of a pattern of the other first wiring line.48. A semiconductor device according to any of claims 43, 44 and 45,wherein the first area is divided into plural second areas and saidplural first wiring lines are disposed in the second areas respectively,the first wiring lines being mutually different in shape.
 49. Asemiconductor device according to any of claims 43, 44 and 45, whereinthe first area is divided into plural second areas and said plural firstwiring lines are disposed in the divided second areas respectively insuch a manner that first wiring line disposed in a predetermined one ofthe plural second areas and the first wiring line disposed in the othersecond area are different in shape.
 50. A semiconductor device accordingto any of claims 43, 44 and 45, wherein the first area is divided intoplural second areas and the first wiring line is disposed in apredetermined one of the plural second areas, while in the other secondarea is disposed a wiring line for supply voltage so as to cover theother second area, the wiring line for supply voltage contributing toactuating an integrated circuit formed in the semiconductor chip.
 51. Asemiconductor device according to claim 50, wherein the first wiringline and the wiring line for supply voltage are disposed in one and samewiring layer.
 52. A semiconductor device according to any of claims 43,44 and 45, wherein said plural detector circuits are connectedelectrically to the first wiring line.
 53. A semiconductor deviceaccording to any of claims 43, 44 and 45, wherein the detector circuitis disposed in an irregular position with respect to the position of thefirst wiring line to which the detector circuit is connected.
 54. Asemiconductor device according to any of claims 43, 44 and 45, whereinthe wiring width and pitch of the first wiring line are set equal tothose of a wiring line which constitutes an integrated circuit formed inthe semiconductor chip.
 55. A semiconductor device according to any ofclaims 43, 44 and 45, wherein the potential of the first wiring line ischanged.
 56. A semiconductor device according to any of claims 43, 44and 45, wherein the potential of the first wiring line is changedirregularly.
 57. A semiconductor device according to any of claims 43,44 and 45, wherein a signal having a predetermined frequency is allowedto flow through the first wiring line and is detected by the detectorcircuit.
 58. A semiconductor device according to any of claims 43, 44and 45, wherein the first wiring line is disposed in a wiring layeroverlying a desired signal line which constitutes an integrated circuitformed in the semiconductor chip.
 59. A semiconductor device comprising:(a) a first area disposed over a main surface of a semiconductor chip;(b) a plurality of second areas formed by dividing the first area; (c) afirst wiring line disposed in a predetermined one of the plural secondareas; (d) a wiring line for supply voltage which contributes toactuating an integrated circuit formed in the semiconductor chip, thewiring line for supply voltage being disposed in the other of the pluralsecond areas so as to cover the other second area, and being differentin shape from the first wiring line; and (e) a detector circuit fordetecting a processing of the first wiring line.
 60. A semiconductordevice comprising: (a) a first area disposed over a main surface of asemiconductor chip; (b) a first wiring line disposed in the first area;(c) a wiring line for supply voltage which contributes to actuating anintegrated circuit formed in the semiconductor chip, and is disposed ina wiring layer different from a wiring layer in which the first wiringline is disposed, the wiring line for supply voltage being disposed inthe first area so as to lie over the first wiring planarly, and beingformed so as to be different in shape from the first wiring line; and(d) a detector circuit for detecting a processing of the first wiringline.
 61. (canceled)
 62. (canceled)
 63. A semiconductor devicecomprising: (a) a first area disposed over a main surface of asemiconductor chip; (b) a first wiring line disposed in the first area;and (c) a detector circuit for detecting a processing of the firstwiring line, wherein said plural first wiring lines different in shapeare disposed in different areas included in the first area. 64.(canceled)
 65. (canceled)
 66. A semiconductor device comprising: (a) afirst area disposed over a main surface of a semiconductor chip; (b) aplurality of second areas formed by dividing the first area; (c) firstwiring lines disposed respectively for the plural second areas; and (d)a detector circuit for detecting a processing of the first wiring lines,wherein the detector circuit is disposed so as to be irregular in apositional relation thereof to the second areas having the first wiringlines to which the detector circuit is connected.
 67. A semiconductordevice according to claim 63, wherein the wiring width and pitch of thefirst wiring lines are set equal to those of a wiring line whichconstitutes an integrated circuit formed over the semiconductor chip.68. A semiconductor device according to claim 63, wherein the potentialof the first wiring lines is changed.
 69. A semiconductor deviceaccording to claim 63, wherein the potential of the first wiring line ischanged irregularly.
 70. A semiconductor device comprising: (a) a firstarea disposed over a main surface of a semiconductor chip; (b) a firstwiring line disposed in the first area; (c) a detector circuit fordetecting a processing of the first wiring line, wherein a signal havinga predetermined frequency is allowed to flow through the first wiringline and is detected by the detector circuit.
 71. A semiconductor devicecomprising: (a) a first area disposed over a main surface of asemiconductor chip; and (b) a first wiring line disposed in the firstarea, wherein the first area is divided into a plurality of secondareas, and said plural first wiring lines disposed respectively in thesecond areas are different in shape.
 72. A semiconductor devicecomprising: (a) a first area disposed over a main surface of asemiconductor chip; (b) a first wiring line disposed in the first area;and (c) a detector circuit for detecting a change in potential of thefirst wiring line, wherein the first area is divided into a plurality ofsecond areas, and said plural first wiring lines disposed respectivelyin the second areas are different in shape.
 73. A semiconductor deviceaccording to claim 72, wherein the detector circuit is disposed in sucha manner that a positional relation thereof to the second area havingthe first wiring line to which the detector circuit is connected becomesirregular.
 74. A semiconductor device comprising: (a) a first areadisposed over a main surface of a semiconductor chip; (b) a plurality ofsecond areas formed by dividing the first area; (c) first wiring linesdisposed respectively in the plural second areas; and (d) a detectorcircuit for detecting a change of a predetermined one of the firstwiring lines disposed in the second areas, wherein the detector circuitis disposed in such a manner that a positional relation thereof to thesecond area having the first wiring line to which the detector circuitis connected becomes irregular.
 75. A semiconductor device comprising:(a) a first area disposed over a main surface of a semiconductor chip;(b) a plurality of second areas formed by dividing the first area; (c)first wiring lines disposed respectively in the plural second areas; and(d) a detector circuit for detecting a change of a predetermined one ofthe first wiring lines disposed in the second areas, wherein the firstwiring lines disposed in the second area are different in shape, andwherein the detector circuit is disposed in such a manner that apositional relation thereof to the second area having the predeterminedfirst wiring line to which the detector circuit is connected becomesirregular.
 76. A semiconductor device according to any one of claims 71to 75, wherein said plural detector circuits are provided for the firstwiring lines.
 77. A semiconductor device according to any of claims 71to 75, wherein the wiring width and pitch of the first wiring lines areset equal to those of a wiring line which constitutes an integratedcircuit formed in the semiconductor chip.
 78. A semiconductor deviceaccording to any of claims 72 to 75, wherein the potential of the firstwiring lines is changed.
 79. A semiconductor device according to any ofclaims 72 to 75, wherein the potential of the first wiring lines ischanged irregularly.
 80. A semiconductor device according to any ofclaims 72 to 75, wherein a signal having a predetermined frequency isallowed to flow through the first wiring lines and is detected by thedetector circuit.
 81. A semiconductor device comprising: (a) a firstarea disposed over a main surface of a semiconductor chip; (b) a firstwiring line having a shielding function and disposed in the first area;and (c) a second wiring line having a shielding function and disposed inthe first area, the second wiring line being formed in a layer differentfrom a layer in which the first wiring line is formed.
 82. Asemiconductor device comprising: (a) a first area disposed over a mainsurface of a semiconductor chip; (b) a first wiring line having ashielding function and disposed in the first area; and (c) a secondwiring line having a shielding function and disposed in the first area,the second wiring line being formed in a layer different from a layer inwhich the first wiring line is formed, wherein the first area is dividedinto a plurality of second areas, said second plural first wiring linesand second wiring lines are disposed in the second area and includethose different in shape.
 83. A semiconductor device comprising: (a) afirst area disposed over a main surface of a semiconductor chip; (b) aplurality of second areas formed by dividing the first area; (c) firstwiring lines disposed respectively in the plural second areas; (d)second wiring lines formed in a layer different from a layer in whichthe first wiring lines are formed, the second wiring lines beingdisposed respectively in the plural second areas; and (e) a firstdetector circuit for detecting a change of a predetermined one of thefirst wiring lines disposed in the second areas, wherein the firstdetector circuit is disposed in such a manner that a positional relationthereof to the second area having the predetermined wiring line to whichthe first detector circuit is connected becomes irregular.
 84. Asemiconductor device comprising: (a) a first area disposed over a mainsurface of a semiconductor chip; (b) a plurality of second areas formedby dividing the first area; (c) first wiring lines disposed respectivelyin the plural second areas; (d) second wiring lines formed in a layerdifferent from a layer in which the first wiring lines are formed, thesecond wiring lines being disposed respectively in the plural secondareas; and (e) a first detector circuit for detecting a change of apredetermined one of the first wiring lines disposed respectively in thesecond areas, wherein the first and second wiring lines disposed in thesecond areas are different in shape, and the first detector circuit isdisposed in such a manner that a positional relation thereof to thesecond area having the predetermined first wiring line to which thefirst detector circuit is connected becomes irregular.
 85. Asemiconductor device according to any of claims 81 to 84, wherein asecond detector circuit for detecting a change of a predetermined one ofthe second wiring lines disposed respectively in the second areas isformed in the predetermined second wiring line.
 86. A semiconductordevice according to any of claims 83 and 84, wherein the first detectorcircuit is disposed in such a manner that a positional relation thereofto the second area having the first wiring line to which the firstdetector circuit is connected becomes irregular.
 87. A semiconductordevice according to any of claims 81 to 84, wherein said plural firstdetector circuits are connected electrically to the first wiring lines.88. A semiconductor device according to any of claims 81 to 84, whereinat least one of the first and second wiring lines is wiring line forsupply voltage to feed a voltage to an integrated circuit formed in thesemiconductor chip.
 89. A semiconductor device comprising: (a) a firstarea disposed over a main surface of a semiconductor chip; (b) a firstwiring line disposed in the first area; and (c) a detector circuit fordetecting a processing of the first wiring line, wherein said pluralfirst wiring lines different in shape are disposed in a mixed statewithin one and same area included in the first area, and wherein thedetector circuit is disposed in such a manner that a positional relationthereof to the first wiring line to which the detector circuit isconnected becomes irregular.